split out instructions from openpower/isa/fparith.mdwn

diff --git a/openpower/isa/fparith.mdwn b/openpower/isa/fparith.mdwn
index 3a238005f0b331247ceb74be012a6e114d19d227..5a6b46d363d3877bc30458d158d413702eb9883f 100644 (file)
--- a/openpower/isa/fparith.mdwn
+++ b/openpower/isa/fparith.mdwn
@@ -2,219 +2,26 @@
 
 <!-- Section 4.6.6.1 Floating-point Elementary Arithmetic p 152-156 -->
 
-# Floating Add [Single]
+[[!inline pagenames="openpower/isa/fparith/fadds" raw="yes"]]
 
-A-Form
+[[!inline pagenames="openpower/isa/fparith/fadd" raw="yes"]]
 
-* fadds FRT,FRA,FRB (Rc=0)
-* fadds. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fparith/fsubs" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fparith/fsub" raw="yes"]]
 
-    FRT <- FPADD32(FRA, FRB)
+[[!inline pagenames="openpower/isa/fparith/fmuls" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fparith/fmul" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fparith/fdivs" raw="yes"]]
 
-# Floating Add [Double]
+[[!inline pagenames="openpower/isa/fparith/fdiv" raw="yes"]]
 
-A-Form
+[[!inline pagenames="openpower/isa/fparith/fmadds" raw="yes"]]
 
-* fadd FRT,FRA,FRB (Rc=0)
-* fadd. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fparith/fmsubs" raw="yes"]]
 
-Pseudo-code:
-
-    FRT <- FPADD64(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Subtract [Single]
-
-A-Form
-
-* fsubs FRT,FRA,FRB (Rc=0)
-* fsubs. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPSUB32(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Subtract [Double]
-
-A-Form
-
-* fsub FRT,FRA,FRB (Rc=0)
-* fsub. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPSUB64(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Multiply [Single]
-
-A-Form
-
-* fmuls FRT,FRA,FRC (Rc=0)
-* fmuls. FRT,FRA,FRC (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMUL32(FRA, FRC)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Multiply [Double]
-
-A-Form
-
-* fmul FRT,FRA,FRC (Rc=0)
-* fmul. FRT,FRA,FRC (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMUL64(FRA, FRC)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Divide [Single]
-
-A-Form
-
-* fdivs FRT,FRA,FRB (Rc=0)
-* fdivs. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPDIV32(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Divide [Double]
-
-A-Form
-
-* fdiv FRT,FRA,FRB (Rc=0)
-* fdiv. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPDIV64(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# Floating Multiply-Add [Single]
-
-A-Form
-
-* fmadds FRT,FRA,FRC,FRB (Rc=0)
-* fmadds. FRT,FRA,FRC,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# Floating Multiply-Sub [Single]
-
-A-Form
-
-* fmsubs FRT,FRA,FRC,FRB (Rc=0)
-* fmsubs. FRT,FRA,FRC,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# Floating Negative Multiply-Add [Single]
-
-A-Form
-
-* fnmadds FRT,FRA,FRC,FRB (Rc=0)
-* fnmadds. FRT,FRA,FRC,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# Floating Negative Multiply-Sub [Single]
-
-A-Form
-
-* fnmsubs FRT,FRA,FRC,FRB (Rc=0)
-* fnmsubs. FRT,FRA,FRC,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fparith/fnmadds" raw="yes"]]
 
+[[!inline pagenames="openpower/isa/fparith/fnmsubs" raw="yes"]]

diff --git a/openpower/isa/fparith/fadd.mdwn b/openpower/isa/fparith/fadd.mdwn
new file mode 100644 (file)
index 0000000..95b0dd1
--- /dev/null
+++ b/openpower/isa/fparith/fadd.mdwn
@@ -0,0 +1,17 @@
+# Floating Add [Double]
+
+A-Form
+
+* fadd FRT,FRA,FRB (Rc=0)
+* fadd. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fadd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fadd_code.mdwn b/openpower/isa/fparith/fadd_code.mdwn
new file mode 100644 (file)
index 0000000..26ab316
--- /dev/null
+++ b/openpower/isa/fparith/fadd_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPADD64(FRA, FRB)

diff --git a/openpower/isa/fparith/fadds.mdwn b/openpower/isa/fparith/fadds.mdwn
new file mode 100644 (file)
index 0000000..ffe5620
--- /dev/null
+++ b/openpower/isa/fparith/fadds.mdwn
@@ -0,0 +1,17 @@
+# Floating Add [Single]
+
+A-Form
+
+* fadds FRT,FRA,FRB (Rc=0)
+* fadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fadds_code.mdwn b/openpower/isa/fparith/fadds_code.mdwn
new file mode 100644 (file)
index 0000000..29e79a6
--- /dev/null
+++ b/openpower/isa/fparith/fadds_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPADD32(FRA, FRB)

diff --git a/openpower/isa/fparith/fdiv.mdwn b/openpower/isa/fparith/fdiv.mdwn
new file mode 100644 (file)
index 0000000..bdd17a6
--- /dev/null
+++ b/openpower/isa/fparith/fdiv.mdwn
@@ -0,0 +1,17 @@
+# Floating Divide [Double]
+
+A-Form
+
+* fdiv FRT,FRA,FRB (Rc=0)
+* fdiv. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fdiv_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fdiv_code.mdwn b/openpower/isa/fparith/fdiv_code.mdwn
new file mode 100644 (file)
index 0000000..af8b44e
--- /dev/null
+++ b/openpower/isa/fparith/fdiv_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPDIV64(FRA, FRB)

diff --git a/openpower/isa/fparith/fdivs.mdwn b/openpower/isa/fparith/fdivs.mdwn
new file mode 100644 (file)
index 0000000..f4b4e5e
--- /dev/null
+++ b/openpower/isa/fparith/fdivs.mdwn
@@ -0,0 +1,17 @@
+# Floating Divide [Single]
+
+A-Form
+
+* fdivs FRT,FRA,FRB (Rc=0)
+* fdivs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fdivs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fdivs_code.mdwn b/openpower/isa/fparith/fdivs_code.mdwn
new file mode 100644 (file)
index 0000000..f194ef1
--- /dev/null
+++ b/openpower/isa/fparith/fdivs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPDIV32(FRA, FRB)

diff --git a/openpower/isa/fparith/fmadds.mdwn b/openpower/isa/fparith/fmadds.mdwn
new file mode 100644 (file)
index 0000000..991ec04
--- /dev/null
+++ b/openpower/isa/fparith/fmadds.mdwn
@@ -0,0 +1,17 @@
+# Floating Multiply-Add [Single]
+
+A-Form
+
+* fmadds FRT,FRA,FRC,FRB (Rc=0)
+* fmadds. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fmadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fmadds_code.mdwn b/openpower/isa/fparith/fmadds_code.mdwn
new file mode 100644 (file)
index 0000000..802e971
--- /dev/null
+++ b/openpower/isa/fparith/fmadds_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)

diff --git a/openpower/isa/fparith/fmsubs.mdwn b/openpower/isa/fparith/fmsubs.mdwn
new file mode 100644 (file)
index 0000000..813b245
--- /dev/null
+++ b/openpower/isa/fparith/fmsubs.mdwn
@@ -0,0 +1,17 @@
+# Floating Multiply-Sub [Single]
+
+A-Form
+
+* fmsubs FRT,FRA,FRC,FRB (Rc=0)
+* fmsubs. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fmsubs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fmsubs_code.mdwn b/openpower/isa/fparith/fmsubs_code.mdwn
new file mode 100644 (file)
index 0000000..0de9d2c
--- /dev/null
+++ b/openpower/isa/fparith/fmsubs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)

diff --git a/openpower/isa/fparith/fmul.mdwn b/openpower/isa/fparith/fmul.mdwn
new file mode 100644 (file)
index 0000000..49923b2
--- /dev/null
+++ b/openpower/isa/fparith/fmul.mdwn
@@ -0,0 +1,17 @@
+# Floating Multiply [Double]
+
+A-Form
+
+* fmul FRT,FRA,FRC (Rc=0)
+* fmul. FRT,FRA,FRC (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fmul_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fmul_code.mdwn b/openpower/isa/fparith/fmul_code.mdwn
new file mode 100644 (file)
index 0000000..b7c97fc
--- /dev/null
+++ b/openpower/isa/fparith/fmul_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPMUL64(FRA, FRC)

diff --git a/openpower/isa/fparith/fmuls.mdwn b/openpower/isa/fparith/fmuls.mdwn
new file mode 100644 (file)
index 0000000..0d73b62
--- /dev/null
+++ b/openpower/isa/fparith/fmuls.mdwn
@@ -0,0 +1,17 @@
+# Floating Multiply [Single]
+
+A-Form
+
+* fmuls FRT,FRA,FRC (Rc=0)
+* fmuls. FRT,FRA,FRC (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fmuls_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fmuls_code.mdwn b/openpower/isa/fparith/fmuls_code.mdwn
new file mode 100644 (file)
index 0000000..bccc48f
--- /dev/null
+++ b/openpower/isa/fparith/fmuls_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPMUL32(FRA, FRC)

diff --git a/openpower/isa/fparith/fnmadds.mdwn b/openpower/isa/fparith/fnmadds.mdwn
new file mode 100644 (file)
index 0000000..9f4f39e
--- /dev/null
+++ b/openpower/isa/fparith/fnmadds.mdwn
@@ -0,0 +1,17 @@
+# Floating Negative Multiply-Add [Single]
+
+A-Form
+
+* fnmadds FRT,FRA,FRC,FRB (Rc=0)
+* fnmadds. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fnmadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fnmadds_code.mdwn b/openpower/isa/fparith/fnmadds_code.mdwn
new file mode 100644 (file)
index 0000000..414d7bd
--- /dev/null
+++ b/openpower/isa/fparith/fnmadds_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)

diff --git a/openpower/isa/fparith/fnmsubs.mdwn b/openpower/isa/fparith/fnmsubs.mdwn
new file mode 100644 (file)
index 0000000..58469f4
--- /dev/null
+++ b/openpower/isa/fparith/fnmsubs.mdwn
@@ -0,0 +1,18 @@
+# Floating Negative Multiply-Sub [Single]
+
+A-Form
+
+* fnmsubs FRT,FRA,FRC,FRB (Rc=0)
+* fnmsubs. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fnmsubs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+

diff --git a/openpower/isa/fparith/fnmsubs_code.mdwn b/openpower/isa/fparith/fnmsubs_code.mdwn
new file mode 100644 (file)
index 0000000..78bfe48
--- /dev/null
+++ b/openpower/isa/fparith/fnmsubs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)

diff --git a/openpower/isa/fparith/fsub.mdwn b/openpower/isa/fparith/fsub.mdwn
new file mode 100644 (file)
index 0000000..66a8330
--- /dev/null
+++ b/openpower/isa/fparith/fsub.mdwn
@@ -0,0 +1,17 @@
+# Floating Subtract [Double]
+
+A-Form
+
+* fsub FRT,FRA,FRB (Rc=0)
+* fsub. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fsub_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fsub_code.mdwn b/openpower/isa/fparith/fsub_code.mdwn
new file mode 100644 (file)
index 0000000..17f6a3a
--- /dev/null
+++ b/openpower/isa/fparith/fsub_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPSUB64(FRA, FRB)

diff --git a/openpower/isa/fparith/fsubs.mdwn b/openpower/isa/fparith/fsubs.mdwn
new file mode 100644 (file)
index 0000000..728dc8f
--- /dev/null
+++ b/openpower/isa/fparith/fsubs.mdwn
@@ -0,0 +1,17 @@
+# Floating Subtract [Single]
+
+A-Form
+
+* fsubs FRT,FRA,FRB (Rc=0)
+* fsubs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fparith/fsubs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fparith/fsubs_code.mdwn b/openpower/isa/fparith/fsubs_code.mdwn
new file mode 100644 (file)
index 0000000..65ebbea
--- /dev/null
+++ b/openpower/isa/fparith/fsubs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- FPSUB32(FRA, FRB)