another big step to a parsable ISA ... no errors after I used a symbolic link for

arch/alpha/main.isa to test my files ...

arch/mips/isa/operands.isa:
    use sd and ud instead of sdw and udw

--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 7e7dfe1d10627031a71761a8f3ef065f502ebee0..6bb5bf4d8f5da50a6216e8b83e695d5d3b031fa2 100644 (file)
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -108,7 +108,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         xc->miscRegs.lo = Rs.uw / Rt.uw;
                         }});
               }
-            };
+            }
 
             0x4: decode FUNCTION_LO {
               format IntOp {
@@ -128,7 +128,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
                 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
               }
-            };
+            }
 
             0x6: decode FUNCTION_LO {
               format Trap {
@@ -144,13 +144,13 @@ decode OPCODE_HI default Unknown::unknown() {
 
         0x1: decode REGIMM_HI {
             0x0: decode REGIMM_LO {
-              format Branch {
-                0x0: bltz({{ cond = (Rs.sq < 0); }});
-                0x1: bgez({{ cond = (Rs.sq >= 0); }});
+              format CondBranch {
+                0x0: bltz({{ cond = (Rs.sw < 0); }});
+                0x1: bgez({{ cond = (Rs.sw >= 0); }});
 
                 //MIPS obsolete instructions
-                0x2: bltzl({{ cond = (Rs.sq < 0); }});
-                0x3: bgezl({{ cond = (Rs.sq >= 0); }});
+                0x2: bltzl({{ cond = (Rs.sw < 0); }});
+                0x3: bgezl({{ cond = (Rs.sw >= 0); }});
               }
             }
 
@@ -166,19 +166,19 @@ decode OPCODE_HI default Unknown::unknown() {
             }
 
             0x2: decode REGIMM_LO {
-              format Branch {
-                0x0: bltzal({{ cond = (Rs.sq < 0); }});
-                0x1: bgezal({{ cond = (Rs.sq >= 0); }});
+              format CondBranch {
+                0x0: bltzal({{ cond = (Rs.sw < 0); }});
+                0x1: bgezal({{ cond = (Rs.sw >= 0); }});
 
                 //MIPS obsolete instructions
-                0x2: bltzall({{ cond = (Rs.sq < 0); }});
-                0x3: bgezall({{ cond = (Rs.sq >= 0); }});
+                0x2: bltzall({{ cond = (Rs.sw < 0); }});
+                0x3: bgezall({{ cond = (Rs.sw >= 0); }});
               }
             }
 
             0x3: decode REGIMM_LO {
               format WarnUnimpl {
-                0x7: synci({{ }});
+                0x7: synci();
               }
             }
         }
@@ -188,13 +188,13 @@ decode OPCODE_HI default Unknown::unknown() {
             0x3: jal(IsCall);
         }
 
-        format Branch {
-            0x4: beq({{ cond = (Rs.sq == 0); }});
-            0x5: bne({{ cond = (Rs.sq !=  0); }});
-            0x6: blez({{ cond = (Rs.sq <= 0); }});
-            0x7: bgtz({{ cond = (Rs.sq > 0); }});
+        format CondBranch {
+            0x4: beq({{ cond = (Rs.sw == 0); }});
+            0x5: bne({{ cond = (Rs.sw !=  0); }});
+            0x6: blez({{ cond = (Rs.sw <= 0); }});
+            0x7: bgtz({{ cond = (Rs.sw > 0); }});
         }
-    };
+    }
 
     0x1: decode OPCODE_LO default FailUnimpl::reserved(){
         format IntOp {
@@ -206,8 +206,8 @@ decode OPCODE_HI default Unknown::unknown() {
             0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
             0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
             0x7: lui({{ Rt = INTIMM << 16}});
-        };
-    };
+        }
+    }
 
     0x2: decode OPCODE_LO default FailUnimpl::reserved(){
 
@@ -336,9 +336,9 @@ decode OPCODE_HI default Unknown::unknown() {
           }
 
           format WarnUnimpl {
-                0x18: eret({{ }});
-                0x1F: deret({{ }});
-                0x20: wait({{ }});
+                0x18: eret();
+                0x1F: deret();
+                0x20: wait();
           }
         }
       }
@@ -360,14 +360,14 @@ decode OPCODE_HI default Unknown::unknown() {
 
           0x1: decode ND {
             0x0: decode TF {
-              format Branch {
+              format CondBranch {
                 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
                 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
               }
             }
 
             0x1: decode TF {
-              format Branch {
+              format CondBranch {
                 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
                 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
               }
@@ -395,7 +395,7 @@ decode OPCODE_HI default Unknown::unknown() {
               }
 
               0x1: decode RS_LO {
-                //only legal for 64 bit
+                //only legal for 64 bit-FP
                 format Float64Op {
                   0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
                   0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
@@ -426,18 +426,21 @@ decode OPCODE_HI default Unknown::unknown() {
 
                 format Float64Op {
                   0x2: recips({{ Fd = 1 / Fs; }});
-                  0x3: rsqrts{{  Fd = 1 / sqrt(Fs); }});
+                  0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
                 }
               }
 
               0x4: decode RS_LO {
-                0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+
+                format FloatOp {
+                  0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
                                 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
                              }});
 
-                0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+                  0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
                                 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
                              }});
+                }
 
                 //only legal for 64 bit
                 format Float64Op {
@@ -467,7 +470,7 @@ decode OPCODE_HI default Unknown::unknown() {
 
               0x1: decode RS_LO {
                 //only legal for 64 bit
-                format FloatOp64 {
+                format Float64Op {
                   0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
                   0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
                   0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
@@ -495,9 +498,9 @@ decode OPCODE_HI default Unknown::unknown() {
                   0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
                 }
 
-                format FloatOp64 {
+                format Float64Op {
                   0x5: recipd({{ Fd.df = 1 / Fs.df}});
-                  0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }});
+                  0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
                 }
               }
 
@@ -515,7 +518,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 }
 
                 //only legal for 64 bit
-                format FloatOp64 {
+                format Float64Op {
                   0x5: cvt_l_d({{
                                 int rnd_mode = xc->miscRegs.fcsr;
                                 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
@@ -561,7 +564,7 @@ decode OPCODE_HI default Unknown::unknown() {
             //are enabled. "
             0x6: decode RS_HI {
               0x0: decode RS_LO {
-                format FloatOp64 {
+                format Float64Op {
                   0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
                                 //Lower Halves Independently but we take simulator shortcut
                                 Fd.df = Fs.df + Ft.df;
@@ -596,23 +599,23 @@ decode OPCODE_HI default Unknown::unknown() {
 
               0x2: decode RS_LO {
                 0x1: decode MOVCF {
-                  format FloatOp64 {
-                    0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
-                    0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
+                  format Float64Op {
+                    0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
+                    0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
                   }
                 }
 
               }
 
               0x4: decode RS_LO {
-                0x0: FloatOp64::cvt_s_pu({{
+                0x0: Float64Op::cvt_s_pu({{
                                 int rnd_mode = xc->miscRegs.fcsr;
                                 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
                            }});
               }
 
               0x5: decode RS_LO {
-                format FloatOp64 {
+                format Float64Op {
                   0x0: cvt_s_pl({{
                                 int rnd_mode = xc->miscRegs.fcsr;
                                 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
@@ -631,27 +634,27 @@ decode OPCODE_HI default Unknown::unknown() {
         0x0: decode RS_HI {
           0x0: decode RS_LO {
             format WarnUnimpl {
-                0x0: mfc2({{ }});
-                0x2: cfc2({{ }});
-                0x3: mfhc2({{ }});
-                0x4: mtc2({{ }});
-                0x6: ctc2({{ }});
-                0x7: mftc2({{ }});
+                0x0: mfc2();
+                0x2: cfc2();
+                0x3: mfhc2();
+                0x4: mtc2();
+                0x6: ctc2();
+                0x7: mftc2();
             }
           }
 
           0x1: decode ND {
             0x0: decode TF {
               format WarnUnimpl {
-                0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
-                0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+                0x0: bc2f();
+                0x1: bc2t();
               }
             }
 
             0x1: decode TF {
               format WarnUnimpl {
-                0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
-                0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+                0x0: bc2fl();
+                0x1: bc2tl();
               }
             }
           }
@@ -681,12 +684,13 @@ decode OPCODE_HI default Unknown::unknown() {
                                 EA = Rs + Rt;
                              }},
                              {{ Mem.df = Ft<63:0>;}});
-                  0x7: prefx({{ }});
                 }
+
+                0x7: WarnUnimpl::prefx();
         }
 
         format FloatOp {
-                0x3: WarnUnimpl::alnv_ps({{ }});
+                0x3: WarnUnimpl::alnv_ps();
 
                 format BasicOp {
                   0x4: decode FUNCTION_LO {
@@ -733,13 +737,13 @@ decode OPCODE_HI default Unknown::unknown() {
       }
 
       //MIPS obsolete instructions
-        format Branch {
-              0x4: beql({{ cond = (Rs.sq == 0); }});
-              0x5: bnel({{ cond = (Rs.sq != 0); }});
-              0x6: blezl({{ cond = (Rs.sq <= 0); }});
-              0x7: bgtzl({{ cond = (Rs.sq > 0); }});
+        format CondBranch {
+              0x4: beql({{ cond = (Rs.sw == 0); }});
+              0x5: bnel({{ cond = (Rs.sw != 0); }});
+              0x6: blezl({{ cond = (Rs.sw <= 0); }});
+              0x7: bgtzl({{ cond = (Rs.sw > 0); }});
         }
-    };
+    }
 
     0x3: decode OPCODE_LO default FailUnimpl::reserved() {
 
@@ -807,7 +811,7 @@ decode OPCODE_HI default Unknown::unknown() {
             }
 
             0x7: decode FUNCTION_LO {
-              0x7: WarnUnimpl::sdbbp({{ }});
+              0x7: WarnUnimpl::sdbbp();
             }
         }
 
@@ -816,15 +820,15 @@ decode OPCODE_HI default Unknown::unknown() {
 
           0x0: decode FUNCTION_LO {
                 format WarnUnimpl {
-                    0x1: ext({{ }});
-                    0x4: ins({{ }});
+                    0x1: ext();
+                    0x4: ins();
                 }
           }
 
           0x1: decode FUNCTION_LO {
                 format WarnUnimpl {
-                    0x0: fork({{ }});
-                    0x1: yield({{ }});
+                    0x0: fork();
+                    0x1: yield();
                 }
           }
 
@@ -832,7 +836,7 @@ decode OPCODE_HI default Unknown::unknown() {
           //Table A-10 MIPS32 BSHFL Encoding of sa Field
           0x4: decode SA {
 
-                0x02: WarnUnimpl::wsbh({{ }});
+                0x02: WarnUnimpl::wsbh();
 
                 format BasicOp {
                     0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24)  | */ Rt<7:0>}});
@@ -844,53 +848,53 @@ decode OPCODE_HI default Unknown::unknown() {
             0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
           }
         }
-    };
+    }
 
     0x4: decode OPCODE_LO default FailUnimpl::reserved() {
         format Memory {
             0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
             0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
-            0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
+            0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign);
             0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
             0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
             0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
-            0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
-        };
+            0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign);
+        }
 
-        0x7: FailUnimpl::reserved({{ }});
-    };
+        0x7: FailUnimpl::reserved();
+    }
 
     0x5: decode OPCODE_LO default FailUnimpl::reserved() {
         format Memory {
             0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
             0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
-            0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
+            0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign);
             0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
-            0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
-        };
+            0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign);
+        }
 
         format WarnUnimpl {
-            0x7: cache({{ }});
-        };
+            0x7: cache();
+        }
 
-    };
+    }
 
     0x6: decode OPCODE_LO default FailUnimpl::reserved() {
-            0x0: WarnUnimpl::ll({{ }});
+            0x0: WarnUnimpl::ll();
 
         format Memory {
             0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
             0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
-        };
-    };
+        }
+    }
 
     0x7: decode OPCODE_LO default FailUnimpl::reserved() {
-        0x0: WarnUnimpl::sc({{ }});
+        0x0: WarnUnimpl::sc();
 
         format Memory {
             0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
             0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
-        };
+        }
 
     }
 }

diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 707109fc280cab3a4a955f1ad8c763e88d03d213..23fcbaa679c427d147e564ab67112e82effa2aac 100644 (file)
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -27,7 +27,7 @@ output decoder {{
         }
 }};
 
-def template FPExecute {{
+def template FloatingPointExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
                 //These are set to constants when the execute method
@@ -70,7 +70,7 @@ def template FPExecute {{
 }};
 
 // Primary format for integer operate instructions:
-def format FPOp(code, *opt_flags) {{
+def format FloatOp(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
         checkPriv = (code.find('checkPriv') != -1)
@@ -86,12 +86,33 @@ def format FPOp(code, *opt_flags) {{
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
+        exec_output = FloatingPointExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format Float64Op(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        checkPriv = (code.find('checkPriv') != -1)
+        code.replace('checkPriv', '')
+        if checkPriv:
+                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+        else:
+                code.replace('checkPriv;', '')
+        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
+                       ('xvValue', '0'), ('xcValue', '0')):
+                code.replace(marker, value)
+        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = FloatingPointExecute.subst(iop)
 }};
 
 // Primary format for integer operate instructions:
 def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
         orig_code = code
+
         cblk = CodeBlock(code)
         checkPriv = (code.find('checkPriv') != -1)
         code.replace('checkPriv', '')

diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 5ed5237c5f99c103f5cee4e1b639b7b63698e35f..e3028eb7cc8d60b0d5fba340ede1ff81fa70c556 100644 (file)
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -55,7 +55,7 @@ def template MemExecute {{
 }};
 
 // Primary format for integer operate instructions:
-def format Mem(code, *opt_flags) {{
+def format Memory(code, ea_code = {{ EA = Rb + disp; }},*opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)

diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index b1ece654d6e7cd5c858f5025018749dc2f39d80e..6d45ba9b6e54dc719a52198c3e56e9bad7ce3c27 100644 (file)
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -45,3 +45,90 @@ def format Noop(code, *opt_flags) {{
         decode_block = BasicDecodeWithMnemonic.subst(iop)
         exec_output = NoopExecute.subst(iop)
 }};
+
+////////////////////////////////////////////////////////////////////
+//
+// Nop
+//
+
+output header {{
+    /**
+     * Static instruction class for no-ops.  This is a leaf class.
+     */
+    class Nop : public AlphaStaticInst
+    {
+        /// Disassembly of original instruction.
+        const std::string originalDisassembly;
+
+      public:
+        /// Constructor
+        Nop(const std::string _originalDisassembly, MachInst _machInst)
+            : AlphaStaticInst("nop", _machInst, No_OpClass),
+              originalDisassembly(_originalDisassembly)
+        {
+            flags[IsNop] = true;
+        }
+
+        ~Nop() { }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+        %(BasicExecDeclare)s
+    };
+}};
+
+output decoder {{
+    std::string Nop::generateDisassembly(Addr pc,
+                                         const SymbolTable *symtab) const
+    {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        return originalDisassembly;
+#else
+        return csprintf("%-10s (%s)", "nop", originalDisassembly);
+#endif
+    }
+
+    /// Helper function for decoding nops.  Substitute Nop object
+    /// for original inst passed in as arg (and delete latter).
+    inline
+    AlphaStaticInst *
+    makeNop(AlphaStaticInst *inst)
+    {
+        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        delete inst;
+        return nop;
+    }
+}};
+
+output exec {{
+    Fault
+    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+    {
+        return No_Fault;
+    }
+}};
+
+// integer & FP operate instructions use Rc as dest, so check for
+// Rc == 31 to detect nops
+def template OperateNopCheckDecode {{
+ {
+     AlphaStaticInst *i = new %(class_name)s(machInst);
+     if (RC == 31) {
+         i = makeNop(i);
+     }
+     return i;
+ }
+}};
+
+
+// Like BasicOperate format, but generates NOP if RC/FC == 31
+def format BasicOperateWithNopCheck(code, *opt_args) {{
+    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
+                        opt_args)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = OperateNopCheckDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+

diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index c8e08a436d80098d4b3b0417dd4606dde86405cf..cf6f10e0bd53776e8fba6a3b29a44ef1150752a4 100644 (file)
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -5,8 +5,8 @@ def operand_types {{
     'uhw' : ('unsigned int', 16),
     'sw' : ('signed int', 32),
     'uw' : ('unsigned int', 32),
-    'sdw' : ('signed int', 64),
-    'udw' : ('unsigned int', 64),
+    'sd' : ('signed int', 64),
+    'ud' : ('unsigned int', 64),
     'sf' : ('float', 32),
     'df' : ('float', 64),
     'qf' : ('float', 128)
@@ -24,7 +24,7 @@ def operands {{
     'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
     'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
 
-    'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+    'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
 
     #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
     #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),