reorg

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 994afb084906e669ef3cefe3a5857280db6e6455..c156ed4adced2440b7760bca63002e603a2b3c1c 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -696,9 +696,7 @@ loop:
 
  \begin{itemize}
    \item Is C.FNE actually needed? Should it be added if it is?
-   \item Element type implies polymorphism.  Should it be in SV?
    \item Should use of registers be allowed to "wrap" (x30 x31 x1 x2)?
-   \item Is detection of all-scalar ops ok (without slowing pipeline)?
    \item Can VSELECT be removed? (it's really complex)
    \item Can CLIP be done as a CSR (mode, like elwidth)
    \item SIMD saturation (etc.) also set as a mode?