etherbone: writes OK on hardware

diff --git a/liteeth/core/etherbone/record.py b/liteeth/core/etherbone/record.py
index 015a0149e000001cbc250e48e6b7522d93e29759..e1ff79769262af96451769d90faa6ad3740b0939 100644 (file)
--- a/liteeth/core/etherbone/record.py
+++ b/liteeth/core/etherbone/record.py
@@ -29,7 +29,7 @@ class LiteEthEtherboneRecordReceiver(Module):
                self.comb += Record.connect(sink, fifo.sink)
 
                self.submodules.base_addr = base_addr = FlipFlop(32)
-               self.comb += base_addr.d.eq(sink.data)
+               self.comb += base_addr.d.eq(fifo.source.data)
 
                self.submodules.counter = counter = Counter(max=512)
 

diff --git a/targets/etherbone.py b/targets/etherbone.py
index aa2047f429811281911582e5140ae93b646d507b..9b305bb5257247410713d30339d8789d0155f08a 100644 (file)
--- a/targets/etherbone.py
+++ b/targets/etherbone.py
@@ -127,6 +127,9 @@ class EtherboneSoC(GenSoC, AutoCSR):
 
                # Etherbone
                self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
+               self.add_wb_master(self.etherbone.master.bus)
+               self.submodules.sram = wishbone.SRAM(1024)
+               self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
 
 class EtherboneSoCDevel(EtherboneSoC, AutoCSR):
        csr_map = {
@@ -163,6 +166,7 @@ class EtherboneSoCDevel(EtherboneSoC, AutoCSR):
                        # etherbone wishbone master
                        self.etherbone.master.bus.dat_w,
                        self.etherbone.master.bus.dat_r,
+                       self.etherbone.master.bus.adr,
                        self.etherbone.master.bus.sel,
                        self.etherbone.master.bus.cyc,
                        self.etherbone.master.bus.stb,

diff --git a/test/test_etherbone.py b/test/test_etherbone.py
index e11773b1954b32fad15a33488c132adf46b3bcc0..68fff21dc40d9cd1c97aa7277dc165b7949c6a14 100644 (file)
--- a/test/test_etherbone.py
+++ b/test/test_etherbone.py
@@ -11,3 +11,24 @@ packet = EtherbonePacket()
 packet.pf = 1
 packet.encode()
 sock.sendto(bytes(packet), ("192.168.1.40", 20000))
+
+# test writes
+writes_datas = [j for j in range(16)]
+writes = EtherboneWrites(base_addr=SRAM_BASE, datas=writes_datas)
+record = EtherboneRecord()
+record.writes = writes
+record.reads = None
+record.bca = 0
+record.rca = 0
+record.rff = 0
+record.cyc = 0
+record.wca = 0
+record.wff = 0
+record.byte_enable = 0xf
+record.wcount = len(writes_datas)
+record.rcount = 0
+
+packet = EtherbonePacket()
+packet.records = [record]
+packet.encode()
+sock.sendto(bytes(packet), ("192.168.1.40", 20000))