projects
/
mesa.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
9a8e4a0
)
radv/gfx10: Only set HW edge flags with gs & tess disabled.
author
Bas Nieuwenhuizen
<bas@basnieuwenhuizen.nl>
Mon, 8 Jul 2019 21:43:34 +0000
(23:43 +0200)
committer
Dave Airlie
<airlied@redhat.com>
Tue, 9 Jul 2019 02:04:23 +0000
(12:04 +1000)
Reviewed-by: Dave Airlie <airlied@redhat.com>
src/amd/vulkan/radv_pipeline.c
patch
|
blob
|
history
diff --git
a/src/amd/vulkan/radv_pipeline.c
b/src/amd/vulkan/radv_pipeline.c
index 1e7c25955fc8daf62edaf4cce2c40e6278dd4c36..5751440f3010353949eb46d850098494965723c0 100644
(file)
--- a/
src/amd/vulkan/radv_pipeline.c
+++ b/
src/amd/vulkan/radv_pipeline.c
@@
-3413,7
+3413,8
@@
radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
* flags in the shader.
*/
radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
- S_028838_INDEX_BUF_EDGE_FLAG_ENA(1));
+ S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
+ !radv_pipeline_has_gs(pipeline)));
radeon_set_context_reg(ctx_cs, R_03096C_GE_CNTL,
S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |