projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
eef0ec6
)
dfflegalize: Gather init values from all wires.
author
Marcelina Kościelnicka
<mwk@0x04.net>
Sun, 12 Jul 2020 13:39:40 +0000
(15:39 +0200)
committer
Marcelina Kościelnicka
<mwk@0x04.net>
Sun, 12 Jul 2020 15:39:13 +0000
(17:39 +0200)
Skipping non-selected wires is unsound in an obvious way.
passes/techmap/dfflegalize.cc
patch
|
blob
|
history
diff --git
a/passes/techmap/dfflegalize.cc
b/passes/techmap/dfflegalize.cc
index c0f112836edf79419bfa6696bd11f861e71b8007..13ce4f49afb39da0705825b7a7e09fbdcd27bbc2 100644
(file)
--- a/
passes/techmap/dfflegalize.cc
+++ b/
passes/techmap/dfflegalize.cc
@@
-1296,7
+1296,7
@@
unrecognized:
sigmap.set(module);
initbits.clear();
- for (auto wire : module->
selected_
wires())
+ for (auto wire : module->wires())
{
if (wire->attributes.count(ID::init) == 0)
continue;