back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index c228611f7722ef0cc700df2544f33ee2556282a6..6db3eaa02fb8a4d47b38c6780dadf1215f772a25 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -513,8 +513,8 @@ class Simulator:
             for domain, cd in self._domains.items():
                 with gtkw_save.group("d.{}".format(domain)):
                     if cd.rst is not None:
-                        gtkw_save.trace("top.{}".format(cd.rst.name))
-                    gtkw_save.trace("top.{}".format(cd.clk.name))
+                        gtkw_save.trace(self._vcd_names[cd.rst])
+                    gtkw_save.trace(self._vcd_names[cd.clk])
 
             for signal in self._gtkw_signals:
                 if signal in self._vcd_names: