Merge branch 'master' into new_soc

diff --cc litex/soc/cores/cpu/__init__.py
index b932d4decd5f6180a89804ab67d641056db71e11,fdb3184e7b6a5c1b22866db59b214adff798c866..3a52fcdbd9cb7e9882984330fe2f90a8dec863ba
--- 1/litex/soc/cores/cpu/__init__.py
--- 2/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@@ -35,9 -33,9 +35,10 @@@ from litex.soc.cores.cpu.vexriscv impor
  from litex.soc.cores.cpu.minerva import Minerva
  from litex.soc.cores.cpu.rocket import RocketRV64
  from litex.soc.cores.cpu.microwatt import Microwatt
+ from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
  
  CPUS = {
 +    "None"       : CPUNone,
      "lm32"       : LM32,
      "mor1kx"     : MOR1KX,
      "picorv32"   : PicoRV32,

diff --cc litex/soc/integration/soc_core.py
index a94426ddd3a479820614369da03be0b09272ef56,b3a103565c7d6f4f17ab184d0da88c16d5d2cebe..8338da15b7540fdfc750d5bdd49cb41fecc0a4cc
--- 1/litex/soc/integration/soc_core.py
--- 2/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@@ -43,10 -46,39 +43,9 @@@ def mem_decoder(address, size=0x1000000
      size    >>= 2 # bytes to words aligned
      return lambda a: (a[log2_int(size):] == (address >> log2_int(size)))
  
 -# SoCController ------------------------------------------------------------------------------------
 -
 -class SoCController(Module, AutoCSR):
 -    def __init__(self):
 -        self._reset      = CSRStorage(1, description="""
 -            Write a ``1`` to this register to reset the SoC.""")
 -        self._scratch    = CSRStorage(32, reset=0x12345678, description="""
 -            Use this register as a scratch space to verify that software read/write accesses
 -            to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
 -            can be used to verify endianness.""")
 -        self._bus_errors = CSRStatus(32, description="""
 -            Total number of Wishbone bus errors (timeouts) since last reset.""")
 -
 -        # # #
 -
 -        # reset
 -        self.reset = Signal()
 -        self.comb += self.reset.eq(self._reset.re)
 -
 -        # bus errors
 -        self.bus_error = Signal()
 -        bus_errors     = Signal(32)
 -        self.sync += \
 -            If(bus_errors != (2**len(bus_errors)-1),
 -                If(self.bus_error,
 -                    bus_errors.eq(bus_errors + 1)
 -                )
 -            )
 -        self.comb += self._bus_errors.status.eq(bus_errors)
--
  # SoCCore ------------------------------------------------------------------------------------------
  
 -class SoCCore(Module):
 +class SoCCore(LiteXSoC):
      # default register/interrupt/memory mappings (can be redefined by user)
      csr_map       = {}
      interrupt_map = {}