(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 98d9c192fcddf4d962fba206492fa80f05dd1db4..c7cebb0f5f80ac86fc6adaa59635a580bf8a263c 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -30,8 +30,10 @@ Modes apply to Arithmetic and Logical SVP64 operations:
 and FP.
 * **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see [[svp64/appendix]]
   note that there are comprehensive caveats when using this mode.
-* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the 
-*destination* predicate bit was zero.  When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  See appendix for details.
+* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch conditional testing) and if the test fails it
+is as if the 
+*destination* predicate bit was zero even before starting the operation. 
+When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  See appendix for details.
 
 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.