convert sv_proc_t::f128 to sv_freg_t type so it carries reg_spec_t state

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index b4bf2e722c391a9032d300edcbd4bf8530072b2b..9a67a739c6e1602e636c8010c2f4ad6fb96238b9 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -612,9 +612,9 @@ sv_float64_t (sv_proc_t::f64)(sv_reg_t const& v)
     return ::f64(x);
 }
 
-sv_float128_t sv_proc_t::f128( float128_t v)
+sv_float128_t sv_proc_t::f128( sv_freg_t v)
 {
-/*
+    uint64_t x = ((float128_t)v).v[0];
     switch (v.get_elwidth())
     {
         // 8-bit
@@ -634,7 +634,6 @@ sv_float128_t sv_proc_t::f128( float128_t v)
         }
         default: break;
     }
-*/
     return ::f128(v);
 }
 

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 90a71de34b1d4e64bb21ae5cc5b4954a29c8b77f..b08840d99965d7a806fb9df8f010553814ea1ea7 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -149,7 +149,7 @@ public:
     sv_reg_t sv_reg_int32(sv_reg_t const&);
 
     // used in conversion of regs FRSn
-    sv_float128_t (f128)(float128_t v);
+    sv_float128_t (f128)(sv_freg_t v);
     sv_float64_t (f64)(sv_freg_t  v);
     sv_float32_t (f32)(sv_freg_t v);