Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d351a6266dce5316c3ecaa8746a2548295b5ed2d..6818edb7a23ac45104683e6052025b101409ad4d 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -33,7 +33,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal;
+bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
 int auto_name_counter, auto_name_offset, auto_name_digits;
 std::map<RTLIL::IdString, int> auto_name_map;
 std::set<RTLIL::IdString> reg_wires, reg_ct;
@@ -1310,7 +1310,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                }
        }
 
-       if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+       if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
                std::stringstream ss;
                dump_reg_init(ss, cell->getPort("\\Q"));
                if (!ss.str().empty()) {
@@ -1607,6 +1607,10 @@ struct VerilogBackend : public Backend {
                log("        without this option all internal cells are converted to Verilog\n");
                log("        expressions.\n");
                log("\n");
+               log("    -siminit\n");
+               log("        add initial statements with hierarchical refs to initialize FFs when\n");
+               log("        in -noexpr mode.\n");
+               log("\n");
                log("    -nodec\n");
                log("        32-bit constant values are by default dumped as decimal numbers,\n");
                log("        not bit pattern. This option deactivates this feature and instead\n");
@@ -1663,6 +1667,7 @@ struct VerilogBackend : public Backend {
                nostr = false;
                defparam = false;
                decimal = false;
+               siminit = false;
                auto_prefix = "";
 
                bool blackboxes = false;
@@ -1739,6 +1744,10 @@ struct VerilogBackend : public Backend {
                                decimal = true;
                                continue;
                        }
+                       if (arg == "-siminit") {
+                               siminit = true;
+                               continue;
+                       }
                        if (arg == "-blackboxes") {
                                blackboxes = true;
                                continue;

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 99ec3e7cddff5b8ad7242167d9c8201ab0f2fd60..0b9aceacc3afe89c5b2c34880700877b175dd9e9 100755 (executable)
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -8,7 +8,7 @@ verbose=false
 keeprunning=false
 makejmode=false
 frontend="verilog"
-backend_opts="-noattr -noexpr"
+backend_opts="-noattr -noexpr -siminit"
 autotb_opts=""
 include_opts=""
 xinclude_opts=""