(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 190dbafe9757f9f461e41a6116a0e2e3196191b7..e2d2f3de7e6f775f63c5e389ac50f4d6ac9b5b81 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -47,7 +47,7 @@ Form: SVL-Form (see [[isatables/fields.text]])
 | -- | -- | --- | ------ | ------ | ------- |--| ------- |
 | 19 | RT | RA  | SVi // | vs ms  | XO[0:4] |Rc| setvl   |
 
-Note that imm (SVi) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero.  Setting bit 22 or 23 causes an illegal exception.
+Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero.  Setting bit 22 or 23 causes an illegal exception.
 
 `ms` - bit 25 - allows for setting of MVL.  `vs` - bit 24 - allows for
 setting of VL.