arch-riscv: Fix disassembling of CSR instructions

The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm

This patch fixes the problem.

Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
index 9a9aa9da444fe201bc5c7224a051f4c34c2ebc12..35f9ccd4b326c87f221ea1d40605baeada765e97 100644 (file)
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -60,13 +60,15 @@ CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
-    if (_numSrcRegs > 0)
-        ss << registerName(_srcRegIdx[0]) << ", ";
     auto data = CSRData.find(csr);
     if (data != CSRData.end())
         ss << data->second.name;
     else
-        ss << "?? (" << hex << "0x" << csr << ")";
+        ss << "?? (" << hex << "0x" << csr << dec << ")";
+    if (_numSrcRegs > 0)
+        ss << ", " << registerName(_srcRegIdx[0]);
+    else
+        ss << uimm;
     return ss.str();
 }