(no commit message)

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index abcd595bd9ca86a4630f7d389ab3a2ce31165fc5..97a6fe1eed1c785f7a2d9966cbdc227021a3125c 100644 (file)
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -41,7 +41,7 @@ registers. The reason why Twin-SVP's prefix is only P48 is because P64 can chang
 
 VL/MVL from a P64 prefix is applied as if a [[specification/sv.setvl]] instruction had been executed as a hidden (first, implicit) instruction in the VBLOCK. This *includes* modification of SV CSR STATE.
 
-itype is described in [[sv_prefix_ptoposal]]. The additional itype on the src operand(s) allows, for example, a LD of 8 bit vectors to be auto-converted to 16 bit signed in a single instruction.  More examples on elwidth polymorphism is in the [[appendix]].
+itype is described in [[sv_prefix_proposal]]. The additional itype on the src operand(s) allows, for example, a LD of 8 bit vectors to be auto-converted to 16 bit signed in a single instruction.  More examples on elwidth polymorphism is in the [[appendix]].
 
 # Rules