SE/FS: Get rid of FULL_SYSTEM in MIPS.

diff --git a/src/arch/mips/BISystem.py b/src/arch/mips/BISystem.py
index a6e4091f25372c8cb37e0a48418afb63543241a3..d5e02485ea97bb844463c36ff3e3b8f135fd1f92 100755 (executable)
--- a/src/arch/mips/BISystem.py
+++ b/src/arch/mips/BISystem.py
@@ -32,10 +32,9 @@ from m5.defines import buildEnv
 
 from System import *
 
-if buildEnv['FULL_SYSTEM']:
-    class BareIronMipsSystem(MipsSystem):
-        type = 'BareIronMipsSystem'
-        system_type = 34
-        system_rev = 1 << 10
-        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class BareIronMipsSystem(MipsSystem):
+    type = 'BareIronMipsSystem'
+    system_type = 34
+    system_rev = 1 << 10
+    hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
 

diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index c8df257e0aef27d784c1b852ceda7591cf569d55..4a0851eba4142ad71c3b2fc68108ed7faed07dee 100644 (file)
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -43,19 +43,18 @@ class MipsSystem(System):
     system_rev = Param.UInt64("Revision of system we are emulating")
     load_addr_mask = 0xffffffffff
 
-if buildEnv['FULL_SYSTEM']:
-    class LinuxMipsSystem(MipsSystem):
-        type = 'LinuxMipsSystem'
-        system_type = 34
-        system_rev = 1 << 10
-
-        boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
-                                             "boot processor frequency")
-
-    class BareIronMipsSystem(MipsSystem):
-        type = 'BareIronMipsSystem'
-        bare_iron = True
-        system_type = 34
-        system_rev = 1 << 10
-        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class LinuxMipsSystem(MipsSystem):
+    type = 'LinuxMipsSystem'
+    system_type = 34
+    system_rev = 1 << 10
+
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+                                         "boot processor frequency")
+
+class BareIronMipsSystem(MipsSystem):
+    type = 'BareIronMipsSystem'
+    bare_iron = True
+    system_type = 34
+    system_rev = 1 << 10
+    hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
 

diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 282845f0d9b8c8ddbc6a32dbaa3dc41a85a17e70..7e2d4b8061690ac8d1d084d88c8a72240f7390f4 100644 (file)
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -33,32 +33,29 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'mips':
+    Source('bare_iron/system.cc')
     Source('dsp.cc')
     Source('faults.cc')
+    Source('idle_event.cc')
     Source('interrupts.cc')
     Source('isa.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
     Source('pagetable.cc')
+    Source('process.cc')
     Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
     Source('tlb.cc')
     Source('utility.cc')
     Source('vtophys.cc')
 
     SimObject('MipsInterrupts.py')
-    DebugFlag('MipsPRA')
+    SimObject('MipsSystem.py')
     SimObject('MipsTLB.py')
 
-    if env['FULL_SYSTEM']:
-        SimObject('MipsSystem.py')
-        Source('idle_event.cc')
-        Source('mips_core_specific.cc')
-        Source('system.cc')
-        Source('stacktrace.cc')
-        Source('linux/system.cc')
-        Source('bare_iron/system.cc')
-    else:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
+    DebugFlag('MipsPRA')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index fc606ad4bcfcf65c7eeaf277655e8cd09e6b0878..524efa178e6ef1a9a7f70f8410eb0fce2520c86c 100644 (file)
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -37,11 +37,8 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
-
-#if !FULL_SYSTEM
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-#endif
 
 namespace MipsISA
 {

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5cef45523b513f64f2de45ce21e653dd9ee40881..1d5f25d6c6116a05e951c6326e7b5fd035fbb8a2 100644 (file)
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -34,7 +34,6 @@
 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
 #define __ARCH_MIPS_ISA_TRAITS_HH__
 
-#include "arch/mips/mips_core_specific.hh"
 #include "arch/mips/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"

diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc
index f82ad8d247c84b2f6feaf678f9428408caaa7b2d..30e0f95e9f1034496c83c5c70d591559afeb267e 100644 (file)
--- a/src/arch/mips/linux/system.cc
+++ b/src/arch/mips/linux/system.cc
@@ -47,6 +47,7 @@
 #include "base/loader/symtab.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Thread.hh"
 #include "dev/platform.hh"
 #include "kern/linux/events.hh"
 #include "kern/linux/printk.hh"
@@ -76,7 +77,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
      * Since we aren't using a bootloader, we have to copy the
      * kernel arguments directly into the kernel's memory.
      */
-    virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
+    virtPort->writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
                 params()->boot_osflags.length()+1);
 
     /**
@@ -85,7 +86,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
      * calculated it by using the PIT, RTC, etc.
      */
     if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort.write(addr, (uint64_t)(SimClock::Frequency /
+        virtPort->write(addr, (uint64_t)(SimClock::Frequency /
                     p->boot_cpu_frequency));
 
     /**
@@ -95,7 +96,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
      * 255 ASNs.
      */
     if (kernelSymtab->findAddress("dp264_mv", addr))
-        virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+        virtPort->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
     else
         panic("could not find dp264_mv\n");
 

diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
deleted file mode 100755 (executable)
index 31d47c8..0000000
--- a/src/arch/mips/mips_core_specific.cc
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2002, 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *          Steve Reinhardt
- */
-
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-
-#if FULL_SYSTEM
-
-////////////////////////////////////////////////////////////////////////
-//
-//  Machine dependent functions
-//
-void
-MipsISA::initCPU(ThreadContext *tc, int cpuId)
-{}
-
-#endif // FULL_SYSTEM || BARE_IRON

diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh
deleted file mode 100644 (file)
index bd66e04..0000000
--- a/src/arch/mips/mips_core_specific.hh
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Jaidev Patwardhan
- */
-
-#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
-#define __ARCH_MIPS_CORE_SPECIFIC_HH__
-
-#include "arch/mips/isa_traits.hh"
-
-class ThreadContext;
-
-namespace MipsISA {
-    void initCPU(ThreadContext *tc, int cpuId);
-};
-
-#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__

diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 1fd15775836365031ad9d68ca8113f45bab406c2..656cb8cbbf0d23f81a607581ee35be102b0aec49 100644 (file)
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -137,12 +137,12 @@
 
 #include "arch/mips/remote_gdb.hh"
 #include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
 #include "cpu/decode.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
 #include "mem/page_table.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace MipsISA;
@@ -158,13 +158,13 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-#if FULL_SYSTEM
-    panic("acc not implemented for MIPS FS!");
-#endif
     TlbEntry entry;
     //Check to make sure the first byte is mapped into the processes address
     //space.
-    return context->getProcessPtr()->pTable->lookup(va, entry);
+    if (FullSystem)
+        panic("acc not implemented for MIPS FS!");
+    else
+        return context->getProcessPtr()->pTable->lookup(va, entry);
 }
 
 /*

diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
index f3bcb5e688dc8338fa1118b94faa9bf30d462111..50f6e1fb06faef66967e080a88a144ea95fee634 100644 (file)
--- a/src/arch/mips/stacktrace.cc
+++ b/src/arch/mips/stacktrace.cc
@@ -37,6 +37,7 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "mem/vport.hh"
 #include "sim/system.hh"
 
 using namespace std;

diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index c1735b74074e753f8e619f1c0eb5e65e9a660994..d367acd6401a034f14f8153625d890c3e68aed2f 100755 (executable)
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -38,6 +38,7 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "mem/physical.hh"
+#include "mem/vport.hh"
 #include "params/MipsSystem.hh"
 #include "sim/byteswap.hh"
 
@@ -45,8 +46,6 @@ using namespace LittleEndianGuest;
 
 MipsSystem::MipsSystem(Params *p) : System(p)
 {
-
-#if FULL_SYSTEM
     if (p->bare_iron == true) {
         hexFile = new HexFile(params()->hex_file_name);
         if (!hexFile->loadSections(functionalPort))
@@ -108,14 +107,12 @@ MipsSystem::MipsSystem(Params *p) : System(p)
     } else {
         panic("could not find hwrpb\n");
     }
-#endif
 }
 
 MipsSystem::~MipsSystem()
 {
 }
 
-#if FULL_SYSTEM
 Addr
 MipsSystem::fixFuncEventAddr(Addr addr)
 {
@@ -126,8 +123,6 @@ void
 MipsSystem::setMipsAccess(Addr access)
 {}
 
-#endif
-
 bool
 MipsSystem::breakpoint()
 {

diff --git a/src/arch/mips/system.hh b/src/arch/mips/system.hh
index 128f365811eef5d791b4be38b6b8bc8c59d2a174..fcaceadcd5c4fe0b4cb9de74c264063cd89c9eda 100755 (executable)
--- a/src/arch/mips/system.hh
+++ b/src/arch/mips/system.hh
@@ -66,7 +66,6 @@ class MipsSystem : public System
      */
     void setMipsAccess(Addr access);
 
-#if FULL_SYSTEM
     /** console symbol table */
     SymbolTable *consoleSymtab;
 
@@ -75,7 +74,6 @@ class MipsSystem : public System
 
     /** Used by some Bare Iron Configurations */
     HexFile *hexFile;
-#endif
 
 #ifndef NDEBUG
   /** Event to halt the simulator if the console calls panic() */
@@ -85,9 +83,7 @@ class MipsSystem : public System
   protected:
     const Params *params() const { return (const Params *)_params; }
 
-
-#if FULL_SYSTEM
-  /** Add a function-based event to the console code. */
+    /** Add a function-based event to the console code. */
     template <class T>
     T *
     addConsoleFuncEvent(const char *lbl)
@@ -96,7 +92,6 @@ class MipsSystem : public System
     }
 
     virtual Addr fixFuncEventAddr(Addr addr);
-#endif
 
 };
 

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 37f71416f8f68131b1d782825fb03ad1f6f83743..7931675ace9c35343b8d50e32ffd4a4a9b7c514f 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -39,11 +39,9 @@
 #include "cpu/thread_context.hh"
 #include "sim/serialize.hh"
 
-#if FULL_SYSTEM
 #include "arch/mips/registers.hh"
 #include "arch/mips/vtophys.hh"
 #include "mem/vport.hh"
-#endif
 
 
 using namespace MipsISA;
@@ -54,23 +52,8 @@ namespace MipsISA {
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
-    if (number < 4) {
-        if (fp)
-            return tc->readFloatRegBits(FirstArgumentReg + number);
-        else
-            return tc->readIntReg(FirstArgumentReg + number);
-    } else {
-        Addr sp = tc->readIntReg(StackPointerReg);
-        VirtualPort *vp = tc->getVirtPort();
-        uint64_t arg = vp->read<uint64_t>(sp +
-                (number - 4) * sizeof(uint64_t));
-        return arg;
-    }
-#else
-    panic("getArgument() is Full system only\n");
+    panic("getArgument() not implemented\n");
     M5_DUMMY_RETURN
-#endif
 }
 
 uint64_t
@@ -253,6 +236,10 @@ startupCPU(ThreadContext *tc, int cpuId)
     tc->activate(0/*tc->threadId()*/);
 }
 
+void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
 void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a2995b098422cb9877e1f37f55fb62713e9e3b11..dc1df067c5509191385cfe3d9a03195cf93118bc 100644 (file)
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -108,6 +108,7 @@ RoundPage(Addr addr)
 // CPU Utility
 //
 void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);

diff --git a/src/dev/mips/malta_cchip.cc b/src/dev/mips/malta_cchip.cc
index e5eafeec22b643cf0f45c7d63026354a5ed6f4ac..25062e422c0e0a82e18273a440103a8e19955932 100755 (executable)
--- a/src/dev/mips/malta_cchip.cc
+++ b/src/dev/mips/malta_cchip.cc
@@ -37,7 +37,6 @@
 #include <string>
 #include <vector>
 
-#include "arch/mips/mips_core_specific.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"