actorlib/spi: fix memory port we/wd

diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py
index 62c742dd4c9e6f95d401150539748d26b414010d..8f44f0b07964e8606f27319b8281ab44e03987c0 100644 (file)
--- a/migen/actorlib/spi.py
+++ b/migen/actorlib/spi.py
@@ -24,7 +24,7 @@ class Collector(Actor):
                dummy = Signal(BV(self._dw))
                wd = Signal(BV(self._dw))
                we = Signal()
-               wp = MemoryPort(wa, dummy, wd, we)
+               wp = MemoryPort(wa, dummy, we, wd)
                ra = Signal(BV(bits_for(self._depth-1)))
                rd = Signal(BV(self._dw))
                rp = MemoryPort(ra, rd)