radeonsi: flush HTILE when appropriate

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 3003dad5e8af0cf18989a5da01d2db67c772ea7f..c21a1013f93fcef57dbd9c1160efe0c51bfbe8e3 100644 (file)
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -197,6 +197,7 @@ void si_context_flush(struct r600_context *ctx, unsigned flags)
        ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
                        R600_CONTEXT_FLUSH_AND_INV_CB_META |
                        R600_CONTEXT_FLUSH_AND_INV_DB |
+                       R600_CONTEXT_FLUSH_AND_INV_DB_META |
                        R600_CONTEXT_INV_TEX_CACHE;
        si_emit_cache_flush(&ctx->b, NULL);
 

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 9b9e97371117b999b20aa43d9fc194439d262f0b..ede8827fe4753184f2e017d82448ad084771d2cf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2099,7 +2099,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                                 R600_CONTEXT_FLUSH_AND_INV_CB_META;
        }
        if (rctx->framebuffer.zsbuf) {
-               rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
+               rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
+                                R600_CONTEXT_FLUSH_AND_INV_DB_META;
        }
 
        util_copy_framebuffer_state(&rctx->framebuffer, state);

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 63df3b555c3c1065d1b99b69ab6a667b3c88c5e0..a3104d0a2666979b3d270ef9a726c7d67fe487e9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -676,6 +676,10 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
                radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
        }
+       if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
+               radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+               radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
+       }
 
        if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
@@ -689,7 +693,7 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato
        rctx->flags = 0;
 }
 
-const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */
+const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
 
 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {