+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (arc_option): Sets all internal gas options when
+ parsing .cpu directive.
+ (declare_register_set): Declare all 64 registers.
+ (md_section_align): Refactor.
+ (md_pcrel_from_section): Remove assert.
+ (pseudo_operand_match): Fix pseudo operand match.
+ (find_reloc): Use flags filed, extend matching.
+ * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
+ relocation.
+
2015-12-01 Alan Modra <amodra@gmail.com>
* config/aout_gnu.h: Invoke aout N_* macros with pointer to
{ "EL", no_argument, NULL, OPTION_EL },
{ "mcpu", required_argument, NULL, OPTION_MCPU },
{ "mA6", no_argument, NULL, OPTION_ARC600 },
- { "mARC600", no_argument, NULL, OPTION_ARC600 },
- { "mARC601", no_argument, NULL, OPTION_ARC601 },
- { "mARC700", no_argument, NULL, OPTION_ARC700 },
+ { "mARC600", no_argument, NULL, OPTION_ARC600 },
+ { "mARC601", no_argument, NULL, OPTION_ARC601 },
+ { "mARC700", no_argument, NULL, OPTION_ARC700 },
{ "mA7", no_argument, NULL, OPTION_ARC700 },
{ "mEM", no_argument, NULL, OPTION_ARCEM },
{ "mHS", no_argument, NULL, OPTION_ARCHS },
c = get_symbol_name (&cpu);
mach = arc_get_mach (cpu);
- restore_line_pointer (c);
if (mach == -1)
goto bad_cpu;
if (!mach_type_specified_p)
{
- arc_mach_type = mach;
+ if ((!strcmp ("ARC600", cpu))
+ || (!strcmp ("ARC601", cpu))
+ || (!strcmp ("A6", cpu)))
+ {
+ md_parse_option (OPTION_MCPU, "arc600");
+ }
+ else if ((!strcmp ("ARC700", cpu))
+ || (!strcmp ("A7", cpu)))
+ {
+ md_parse_option (OPTION_MCPU, "arc700");
+ }
+ else if (!strcmp ("EM", cpu))
+ {
+ md_parse_option (OPTION_MCPU, "arcem");
+ }
+ else if (!strcmp ("HS", cpu))
+ {
+ md_parse_option (OPTION_MCPU, "archs");
+ }
+ else
+ as_fatal ("could not find the architecture");
+
if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
as_fatal ("could not set architecture and machine");
-
- mach_type_specified_p = 1;
}
else
if (arc_mach_type != mach)
as_warn ("Command-line value overrides \".cpu\" directive");
+ restore_line_pointer (c);
demand_empty_rest_of_line ();
-
return;
bad_cpu:
+ restore_line_pointer (c);
as_bad ("invalid identifier for \".cpu\"");
ignore_rest_of_line ();
}
declare_register_set (void)
{
int i;
- for (i = 0; i < 32; ++i)
+ for (i = 0; i < 64; ++i)
{
char name[7];
{
int align = bfd_get_section_alignment (stdoutput, segment);
- return ((size + (1 << align) - 1) & -(1 << align));
+ return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
}
/* The location from which a PC relative jump should be calculated,
case BFD_RELOC_ARC_PC32:
/* The hardware calculates relative to the start of the
insn, but this relocation is relative to location of the
- LIMM, compensate. TIP: the base always needs to be
+ LIMM, compensate. The base always needs to be
substracted by 4 as we do not support this type of PCrel
relocation for short instructions. */
- base -= fixP->fx_where - fixP->fx_dot_value;
- gas_assert ((fixP->fx_where - fixP->fx_dot_value) == 4);
+ base -= 4;
/* Fall through. */
case BFD_RELOC_ARC_PLT32:
case BFD_RELOC_ARC_S25H_PCREL_PLT:
ret = 1;
else if (!(operand_real->flags & ARC_OPERAND_IR))
{
- val = tok->X_add_number;
+ val = tok->X_add_number + op->count;
if (operand_real->flags & ARC_OPERAND_SIGNED)
{
max = (1 << (operand_real->bits - 1)) - 1;
{
unsigned int i;
int j;
- bfd_boolean found_flag;
+ bfd_boolean found_flag, tmp;
extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
for (i = 0; i < arc_num_equiv_tab; i++)
continue;
if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
continue;
- if (r->flagcode)
+ if (r->flags[0])
{
if (!nflg)
continue;
found_flag = FALSE;
- for (j = 0; j < nflg; j++)
- if (pflags[i].code == r->flagcode)
- {
- found_flag = TRUE;
- break;
- }
+ unsigned * psflg = (unsigned *)r->flags;
+ do
+ {
+ tmp = FALSE;
+ for (j = 0; j < nflg; j++)
+ if (!strcmp (pflags[j].name,
+ arc_flag_operands[*psflg].name))
+ {
+ tmp = TRUE;
+ break;
+ }
+ if (!tmp)
+ {
+ found_flag = FALSE;
+ break;
+ }
+ else
+ {
+ found_flag = TRUE;
+ }
+ ++ psflg;
+ } while (*psflg);
+
if (!found_flag)
continue;
}
arc_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC))
/* We don't want gas to fixup the following program memory related
- relocations. */
-#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \
- if ((FIXP->fx_r_type == BFD_RELOC_ARC_GOTPC32) \
- && FIXP->fx_addsy != NULL \
- && FIXP->fx_subsy == NULL) \
- { \
- symbol_mark_used_in_reloc (FIXP->fx_addsy); \
- goto SKIP; \
+ relocations. Check also that fx_addsy is not NULL, in order to
+ make sure that the fixup refers to some sort of label. */
+#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \
+ if ((FIXP->fx_r_type == BFD_RELOC_ARC_GOTPC32 \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_PLT32 \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_S25W_PCREL_PLT \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_S25H_PCREL_PLT \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_S21W_PCREL_PLT \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_S21H_PCREL_PLT) \
+ && FIXP->fx_addsy != NULL \
+ && FIXP->fx_subsy == NULL) \
+ { \
+ symbol_mark_used_in_reloc (FIXP->fx_addsy); \
+ goto SKIP; \
}
/* BFD_RELOC_ARC_TLS_GD_LD may use fx_subsy to store a label that is
+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * gas/arc/bic.d: Update test.
+ * gas/arc/add_s-err.s: New file.
+ * gas/arc/cpu-warn1.s: Likewise.
+ * gas/arc/pcl-relocs.d: Likewise.
+ * gas/arc/pcl-relocs.s: Likewise.
+ * gas/arc/pcrel-relocs.d: Likewise.
+ * gas/arc/pcrel-relocs.s: Likewise.
+ * gas/arc/pic-relocs.d: Likewise.
+ * gas/arc/pic-relocs.s: Likewise.
+ * gas/arc/plt-relocs.d: Likewise.
+ * gas/arc/plt-relocs.s: Likewise.
+ * gas/arc/pseudos.d: Likewise.
+ * gas/arc/pseudos.s: Likewise.
+ * gas/arc/sda-relocs.d: Likewise.
+ * gas/arc/sda-relocs.s: Likewise.
+ * gas/arc/sda-relocs2.d: Likewise.
+ * gas/arc/sda-relocs2.s: Likewise.
+ * gas/arc/tls-relocs.d: Likewise.
+ * gas/arc/tls-relocs.s: Likewise.
+
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ...
--- /dev/null
+;; Test ARC EM Code denisty ADD_S extensions. They are only valid for
+;; ARCv2 architecture.
+;;
+; { dg-do assemble { target arc-*-* } }
+; { dg-options "--mcpu=arc700" }
+ ;; The following insns are accepted by ARCv2 only
+ add_s r4,r4,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
+ add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
+ add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
+ add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
68: ARC_32_ME foo
0x[0-9a-f]+ 20c6 0080 bic r0,r0,r2
0x[0-9a-f]+ 23c6 0140 bic r3,r3,r5
-0x[0-9a-f]+ 26c6 0201 biceq r6,r6,r8
-0x[0-9a-f]+ 21c6 12c1 biceq r9,r9,r11
-0x[0-9a-f]+ 24c6 1382 bicne r12,r12,r14
-0x[0-9a-f]+ 27c6 1442 bicne r15,r15,r17
-0x[0-9a-f]+ 22c6 2503 bicp r18,r18,r20
-0x[0-9a-f]+ 25c6 25c3 bicp r21,r21,r23
-0x[0-9a-f]+ 20c6 3684 bicn r24,r24,gp
-0x[0-9a-f]+ 23c6 3744 bicn fp,fp,ilink
-0x[0-9a-f]+ 26c6 37c5 bicc r30,r30,blink
-0x[0-9a-f]+ 23c6 00c5 bicc r3,r3,r3
-0x[0-9a-f]+ 23c6 0205 bicc r3,r3,r8
-0x[0-9a-f]+ 23c6 0106 bicnc r3,r3,r4
-0x[0-9a-f]+ 24c6 0106 bicnc r4,r4,r4
-0x[0-9a-f]+ 24c6 01c6 bicnc r4,r4,r7
-0x[0-9a-f]+ 24c6 0147 bicv r4,r4,r5
-0x[0-9a-f]+ 25c6 0147 bicv r5,r5,r5
-0x[0-9a-f]+ 25c6 0148 bicnv r5,r5,r5
-0x[0-9a-f]+ 25c6 0148 bicnv r5,r5,r5
-0x[0-9a-f]+ 26c6 0009 bicgt r6,r6,r0
-0x[0-9a-f]+ 20c6 002a bicge r0,r0,0
-0x[0-9a-f]+ 21c6 006b biclt r1,r1,0x1
-0x[0-9a-f]+ 23c6 00ed bichi r3,r3,0x3
-0x[0-9a-f]+ 24c6 012e bicls r4,r4,0x4
-0x[0-9a-f]+ 25c6 016f bicpnz r5,r5,0x5
+0x[0-9a-f]+ 26c6 0201 bic.eq r6,r6,r8
+0x[0-9a-f]+ 21c6 12c1 bic.eq r9,r9,r11
+0x[0-9a-f]+ 24c6 1382 bic.ne r12,r12,r14
+0x[0-9a-f]+ 27c6 1442 bic.ne r15,r15,r17
+0x[0-9a-f]+ 22c6 2503 bic.p r18,r18,r20
+0x[0-9a-f]+ 25c6 25c3 bic.p r21,r21,r23
+0x[0-9a-f]+ 20c6 3684 bic.n r24,r24,gp
+0x[0-9a-f]+ 23c6 3744 bic.n fp,fp,ilink
+0x[0-9a-f]+ 26c6 37c5 bic.c r30,r30,blink
+0x[0-9a-f]+ 23c6 00c5 bic.c r3,r3,r3
+0x[0-9a-f]+ 23c6 0205 bic.c r3,r3,r8
+0x[0-9a-f]+ 23c6 0106 bic.nc r3,r3,r4
+0x[0-9a-f]+ 24c6 0106 bic.nc r4,r4,r4
+0x[0-9a-f]+ 24c6 01c6 bic.nc r4,r4,r7
+0x[0-9a-f]+ 24c6 0147 bic.v r4,r4,r5
+0x[0-9a-f]+ 25c6 0147 bic.v r5,r5,r5
+0x[0-9a-f]+ 25c6 0148 bic.nv r5,r5,r5
+0x[0-9a-f]+ 25c6 0148 bic.nv r5,r5,r5
+0x[0-9a-f]+ 26c6 0009 bic.gt r6,r6,r0
+0x[0-9a-f]+ 20c6 002a bic.ge r0,r0,0
+0x[0-9a-f]+ 21c6 006b bic.lt r1,r1,0x1
+0x[0-9a-f]+ 23c6 00ed bic.hi r3,r3,0x3
+0x[0-9a-f]+ 24c6 012e bic.ls r4,r4,0x4
+0x[0-9a-f]+ 25c6 016f bic.pnz r5,r5,0x5
0x[0-9a-f]+ 2106 8080 bic.f r0,r1,r2
0x[0-9a-f]+ 2146 8040 bic.f r0,r1,0x1
0x[0-9a-f]+ 2606 f080 0000 0001 bic.f r0,0x1,r2
0x[0-9a-f]+ 2106 80be bic.f 0,r1,r2
0x[0-9a-f]+ 2106 8f80 0000 0200 bic.f r0,r1,0x200
0x[0-9a-f]+ 2606 f080 0000 0200 bic.f r0,0x200,r2
-0x[0-9a-f]+ 21c6 8081 bic.feq r1,r1,r2
-0x[0-9a-f]+ 20c6 8022 bic.fne r0,r0,0
-0x[0-9a-f]+ 22c6 808b bic.flt r2,r2,r2
-0x[0-9a-f]+ 26c6 f0a9 0000 0001 bic.fgt 0,0x1,0x2
-0x[0-9a-f]+ 26c6 ff8c 0000 0200 bic.fle 0,0x200,0x200
-0x[0-9a-f]+ 26c6 f0aa 0000 0200 bic.fge 0,0x200,0x2
+0x[0-9a-f]+ 21c6 8081 bic.f.eq r1,r1,r2
+0x[0-9a-f]+ 20c6 8022 bic.f.ne r0,r0,0
+0x[0-9a-f]+ 22c6 808b bic.f.lt r2,r2,r2
+0x[0-9a-f]+ 26c6 f0a9 0000 0001 bic.f.gt 0,0x1,0x2
+0x[0-9a-f]+ 26c6 ff8c 0000 0200 bic.f.le 0,0x200,0x200
+0x[0-9a-f]+ 26c6 f0aa 0000 0200 bic.f.ge 0,0x200,0x2
--- /dev/null
+; Test mismatch between cpu option passed by mcpu option and .cpu
+; directive option.
+; { dg-do assemble }
+; { dg-options "--mcpu=arc700" }
+ .cpu EM; { dg-warning "Warning: Command-line value overrides \".cpu\" directive" }
--- /dev/null
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
+ 4: ARC_PC32 var
+0x[0-9a-f]+ 2736 7f86 0000 0000 ldd r6r7,\[pcl,0\]
+ c: ARC_PC32 var
+0x[0-9a-f]+ 2730 7f83 0000 0000 ld r3,\[pcl,0\]
+ 14: ARC_PC32 var
--- /dev/null
+;;; Test if the assembler correctly generates @pcl relocations
+ .cpu HS
+ .text
+ add r0,pcl,@var@pcl
+ ldd r6,[pcl,@var@pcl]
+ ld r3,[pcl,@var@pcl]
--- /dev/null
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ 0000 0002 bne 0
+ 0: ARC_S21H_PCREL printf
+0x[0-9a-f]+ 0800 0002 blne 0x00000000
+ 4: ARC_S21W_PCREL printf
+0x[0-9a-f]+ 0001 0000 b 0x00000000
+ 8: ARC_S25H_PCREL printf
+0x[0-9a-f]+ 0802 0000 bl 0x00000000
+ c: ARC_S25W_PCREL printf
+0x[0-9a-f]+ f800 bl_s 0x00000000
+ 10: ARC_S13_PCREL printf
--- /dev/null
+;;; Test if the assembler correctly generates PC-relative relocations
+;;; related with branch instructions
+ .cpu HS
+ .text
+ bne @printf
+ blne @printf
+ b @printf
+ bl @printf
+ bl_s @printf
--- /dev/null
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\]
+ 4: ARC_GOTPC32 var
+0x[0-9a-f]+ 2700 7f9a 0000 0000 add gp,pcl,0
+ c: ARC_GOTPC32 var
+0x[0-9a-f]+ 2200 3f82 0000 0000 add r2,gp,0
+ 14: ARC_GOTOFF var
--- /dev/null
+;;; Test if the assembler correctly generates @pcl relocations
+ .cpu HS
+ .text
+ ld r2,[pcl,@var@gotpc]
+ add gp,pcl,@var@gotpc
+
+ add r2,gp,@var@gotoff
--- /dev/null
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ 0000 0002 bne 0
+ 0: ARC_S21H_PCREL_PLT printf
+0x[0-9a-f]+ 0800 0002 blne 0x00000000
+ 4: ARC_S21W_PCREL_PLT printf
+0x[0-9a-f]+ 0001 0000 b 0x00000000
+ 8: ARC_S25H_PCREL_PLT printf
+0x[0-9a-f]+ 0802 0000 bl 0x00000000
+ c: ARC_S25W_PCREL_PLT printf
+0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
+ 14: ARC_PLT32 printf
--- /dev/null
+;;; Test if the assembler correctly generates PC-relative relocations
+;;; related with branch instructions
+ .cpu HS
+ .text
+ bne @printf@plt
+ blne @printf@plt
+ b @printf@plt
+ bl @printf@plt
+ add r0,pcl,@printf@plt
--- /dev/null
+#as:
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 1cfc b008 st.aw r0,\[sp,-4\]
+ 4: 1404 3401 ld.ab r1,\[sp,4\]
+ 8: 0901 0002 brlt.* r1,r0,0x8
+ c: 08fd 8013 brge.* r0,0,0x8
+ 10: 0ef9 f002 0000 003f brlt.* 0x3f,r0,0x8
+ 18: 0ef1 f002 ffff fffe brlt.* 0xfffffffe,r0,0x8
+ 20: 08e9 8f82 ffff fffe brlt.* r0,0xfffffffe,0x8
+ 28: 0ee1 f013 ffff fffe brge.* 0xfffffffe,0,0x8
+ 30: 0ed9 ffd3 ffff fffe brge.* 0xfffffffe,0x3f,0x8
+ 38: 09d1 8044 brlo.* r1,r1,0x8
+ 3c: 09cd 8015 brhs.* r1,0,0x8
+ 40: 0ec9 f044 0000 003f brlo.* 0x3f,r1,0x8
+ 48: 0ec1 f044 ffff fffe brlo.* 0xfffffffe,r1,0x8
+ 50: 08b9 8f84 ffff fffe brlo.* r0,0xfffffffe,0x8
+ 58: 0eb1 f015 ffff fffe brhs.* 0xfffffffe,0,0x8
+ 60: 0ea9 ffd5 ffff fffe brhs.* 0xfffffffe,0x3f,0x8
+ 68: 09a1 8043 brge.* r1,r1,0x8
+ 6c: 099d 8012 brlt.* r1,0,0x8
+ 70: 0e99 f043 0000 003f brge.* 0x3f,r1,0x8
+ 78: 0e91 f043 ffff fffe brge.* 0xfffffffe,r1,0x8
+ 80: 0889 8f83 ffff fffe brge.* r0,0xfffffffe,0x8
+ 88: 0e81 f012 ffff fffe brlt.* 0xfffffffe,0,0x8
+ 90: 0e79 ffd2 ffff fffe brlt.* 0xfffffffe,0x3f,0x8
+ 98: 0971 8043 brge.* r1,r1,0x8
+ 9c: 096d 8012 brlt.* r1,0,0x8
+ a0: 0e69 f043 0000 003f brge.* 0x3f,r1,0x8
+ a8: 0e61 f043 ffff fffe brge.* 0xfffffffe,r1,0x8
+ b0: 0859 8f83 ffff fffe brge.* r0,0xfffffffe,0x8
+ b8: 0e51 f012 ffff fffe brlt.* 0xfffffffe,0,0x8
+ c0: 0e49 ffd2 ffff fffe brlt.* 0xfffffffe,0x3f,0x8
--- /dev/null
+# Test pseudo instructions generation.
+ push r0
+ pop r1
+.L1:
+ brgt r0, r1, @.L1 ; Encode as BRLT<.d> c,b,s9
+ brgt r0, -1, @.L1 ; Encode as BRGE<.d> b,u6+1,s9
+ brgt r0, 0x3F, @.L1 ; Encode as BRLT limm,b,s9
+ brgt r0, -2, @.L1 ; Encode as BRLT limm,b,s9
+ brgt -2, r0, @.L1 ; Encode as BRLT c,limm,s9
+ brgt -2, -1, @.L1 ; Encode as BRGE limm,u6+1,s9
+ brgt -2, 0x3E, @.L1 ; Encode as BRGE limm,u6+1,s9
+
+ brhi r1, r1, @.L1 ; BRHI<.d> b,c,s9 Encode as BRLO<.d> c,b,s9
+ brhi r1, -1, @.L1 ; BRHI<.d> b,u6,s9 Encode as BRHS<.d> b,u6+1,s9
+ brhi r1, 0x3F, @.L1 ; BRHI b,limm,s9 Encode as BRLO limm,b,s9
+ brhi r1, -2, @.L1 ; BRHI b,limm,s9 Encode as BRLO limm,b,s9
+ brhi -2, r0, @.L1 ; BRHI limm,c,s9 Encode as BRLO c,limm,s9
+ brhi -2, -1, @.L1 ; BRHI limm,u6,s9 Encode as BRHS limm,u6+1,s9
+ brhi -2, 0x3E, @.L1 ; BRHI limm,u6,s9 Encode as BRHS limm,u6+1,s9
+
+ brle r1, r1, @.L1 ; BRLE<.d> b,c,s9 Encode as BRGE<.d> c,b,s9
+ brle r1, -1, @.L1 ; BRLE<.d> b,u6,s9 Encode as BRLT<.d> b,u6+1,s9
+ brle r1, 0x3F, @.L1 ; BRLE b,limm,s9 Encode as BRGE limm,b,s9
+ brle r1, -2, @.L1 ; BRLE b,limm,s9 Encode as BRGE limm,b,s9
+ brle -2, r0, @.L1 ; BRLE limm,c,s9 Encode as BRGE c,limm,s9
+ brle -2, -1, @.L1 ; BRLE limm,u6,s9 Encode as BRLT limm,u6+1,s9
+ brle -2, 0x3E, @.L1 ; BRLE limm,u6,s9 Encode as BRLT limm,u6+1,s9
+
+ brle r1, r1, @.L1 ; BRLS<.d> b,c,s9 Encode as BRHS<.d> c,b,s9
+ brle r1, -1, @.L1 ; BRLS<.d> b,u6,s9 Encode as BRLO b,u6+1,s9
+ brle r1, 0x3F, @.L1 ; BRLS b,limm,s9 Encode as BRHS limm,b,s9
+ brle r1, -2, @.L1 ; BRLS limm,c,s9 Encode as BRHS c,limm,s9
+ brle -2, r0, @.L1 ; BRLS limm,c,s9 Encode as BRHS c,limm,s9
+ brle -2, -1, @.L1 ; BRLS limm,u6,s9 Encode as BRLO limm,u6+1,s9
+ brle -2, 0x3E, @.L1 ; BRLS limm,u6,s9 Encode as BRLO limm,u6+1,s9
--- /dev/null
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ ce00 add_s r0,gp,0
+ 0: ARC_SDA16_LD2 a
+0x[0-9a-f]+ c800 ld_s r0,\[gp,0\]
+ 2: ARC_SDA16_LD2 a
+0x[0-9a-f]+ cc00 ldw_s r0,\[gp,0\]
+ 4: ARC_SDA16_LD1 a
+0x[0-9a-f]+ ca00 ldb_s r0,\[gp,0\]
+ 6: ARC_SDA16_LD a
+0x[0-9a-f]+ 1200 360c ld.as r12,\[gp\]
+ 8: ARC_SDA_LDST2 a
+0x[0-9a-f]+ 1a00 3398 st.as r14,\[gp\]
+ c: ARC_SDA_LDST2 a
+0x[0-9a-f]+ 1200 300a ld r10,\[gp\]
+ 10: ARC_SDA_LDST a
+0x[0-9a-f]+ 1a00 3240 st r9,\[gp\]
+ 14: ARC_SDA_LDST a
+0x[0-9a-f]+ 1200 3108 ldh r8,\[gp\]
+ 18: ARC_SDA_LDST a
+0x[0-9a-f]+ 1a00 31c4 sth r7,\[gp\]
+ 1c: ARC_SDA_LDST a
+0x[0-9a-f]+ 1200 3086 ldb r6,\[gp\]
+ 20: ARC_SDA_LDST a
+0x[0-9a-f]+ 1a00 3142 stb r5,\[gp\]
+ 24: ARC_SDA_LDST a
+0x[0-9a-f]+ 1200 3708 ldh.as r8,\[gp\]
+ 28: ARC_SDA_LDST1 a
+0x[0-9a-f]+ 1a00 31dc sth.as r7,\[gp\]
+ 2c: ARC_SDA_LDST1 a
+0x[0-9a-f]+ 1200 3688 ldb.as r8,\[gp\]
+ 30: ARC_SDA_LDST a
+0x[0-9a-f]+ 1a00 31da stb.as r7,\[gp\]
+ 34: ARC_SDA_LDST a
+0x[0-9a-f]+ 2200 3f81 0000 0000 add r1,gp,0
+ 3c: ARC_SDA32_ME a
--- /dev/null
+;;; Test if the assembler generates correctly all SDA relocations.
+
+ .cpu ARC700
+ .text
+ ;; BFD_RELOC_ARC_SDA16_LD2 (s11 range)
+ add_s r0,gp,@a@sda
+ ld_s r0,[gp,@a@sda]
+
+ ;; BFD_RELOC_ARC_SDA16_LD1 (s10 range)
+ ldw_s r0,[gp,@a@sda]
+
+ ;; BFD_RELOC_ARC_SDA16_LD (s9 range)
+ ldb_s r0,[gp,@a@sda]
+
+ ;; BFD_RELOC_ARC_SDA_LDST2 (s11 range)
+ ld.as r12,[gp,@a@sda]
+ st.as r14,[gp,@a@sda]
+
+ ;; BFD_RELOC_ARC_SDA_LDST (s9 range)
+ ld r10,[gp,@a@sda]
+ st r9,[gp,@a@sda]
+ ldw r8,[gp,@a@sda]
+ stw r7,[gp,@a@sda]
+ ldb r6,[gp,@a@sda]
+ stb r5,[gp,@a@sda]
+
+ ;; BFD_RELOC_ARC_SDA_LDST1 (s10 range)
+ ldw.as r8,[gp,@a@sda]
+ stw.as r7,[gp,@a@sda]
+
+ ;; Undefined behavior. However it should be something like: LDST
+ ldb.as r8,[gp,@a@sda]
+ stb.as r7,[gp,@a@sda]
+
+ ;; BFD_RELOC_ARC_SDA_ME
+ add r1,gp,@a@sda
--- /dev/null
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ 1200 3180 ldd r0r1,\[gp\]
+ 0: ARC_SDA_LDST b
+0x[0-9a-f]+ 1a00 3086 std r2r3,\[gp\]
+ 4: ARC_SDA_LDST b
+0x[0-9a-f]+ 1200 3780 ldd.as r0r1,\[gp\]
+ 8: ARC_SDA_LDST2 b
+0x[0-9a-f]+ 1a00 309e std.as r2r3,\[gp\]
+ c: ARC_SDA_LDST2 b
+0x[0-9a-f]+ 5000 ld_s r1,\[gp,0\]
+ 10: ARC_SDA16_ST2 b
+0x[0-9a-f]+ 5010 st_s r0,\[gp,0\]
+ 12: ARC_SDA16_ST2 b
--- /dev/null
+;;; Test if the assembler generates correctly all SDA relocations.
+
+ .cpu HS
+ .text
+ ;; BFD_RELOC_ARC_SDA_LDST (s9 range)
+ ldd r0,[gp,@b@sda]
+ std r2,[gp,@b@sda]
+
+ ;; BFD_RELOC_ARC_SDA_LDST2 (s11 range)
+ ldd.as r0,[gp,@b@sda]
+ std.as r2,[gp,@b@sda]
+
+ ;; BFD_RELOC_ARC_SDA16_ST2 (s11 range)
+ ld_s r1,[gp,@b@sda]
+ st_s r0,[gp,@b@sda]
--- /dev/null
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\]
+ 4: ARC_TLS_IE_GOT var
+0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
+ c: ARC_TLS_GD_GOT var
+0x[0-9a-f]+ 2000 0f81 0000 0000 add r1,r0,0
+ 14: ARC_TLS_DTPOFF var
+0x[0-9a-f]+ 2100 3f80 0000 0000 add r0,r25,0
+ 1c: ARC_TLS_LE_32 var
+0x[0-9a-f]+ 0802 0000 bl 0x00000000
+ 20: ARC_TLS_GD_LD .tdata
+ 20: ARC_S25W_PCREL_PLT func
--- /dev/null
+;;; Test if the assembler correctly generates TLS relocations
+
+ .cpu HS
+ .text
+ ;; RELOC_ARC_TLS_IE_GOT
+ ld r2,[pcl,@var@tlsie]
+
+ ;; RELOC_ARC_TLS_GD_GOT
+ add r0,pcl,@var@tlsgd
+
+ ;; RELOC_ARC_TLS_DTPOFF
+ add r1,r0,@var@dtpoff
+
+ ;; RELOC_ARC_TLS_LE_32
+ add r0,r25,@var@tpoff
+
+ ;; RELOC_ARC_TLS_GD_LD
+ .tls_gd_ld @.tdata`bl @func@plt
+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
+
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_op): Add OP_BFC.
{
const char * name; /* String to lookup. */
const char * mnemonic; /* Extra matching condition. */
- unsigned flagcode; /* Extra matching condition. */
+ unsigned flags[32]; /* Extra matching condition. */
signed int oldreloc; /* Old relocation. */
signed int newreloc; /* New relocation. */
};
+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (special_flag_p): Match full mnemonic.
+ * arc-opc.c (print_insn_arc): Check section size to read
+ appropriate number of bytes. Fix printing.
+ * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
+ arguments.
+
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
const char *flgname)
{
const struct arc_flag_special *flg_spec;
- size_t len;
unsigned i, j, flgidx;
for (i = 0; i < arc_num_flag_special; i++)
{
flg_spec = &arc_flag_special_cases[i];
- len = strlen (flg_spec->name);
- if (strncmp (opname, flg_spec->name, len) != 0)
+ if (strcmp (opname, flg_spec->name))
continue;
/* Found potential special case instruction. */
int flags;
bfd_boolean need_comma;
bfd_boolean open_braket;
-
+ int size;
lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
break;
}
+ /* This variable may be set by the instruction decoder. It suggests
+ the number of bytes objdump should display on a single line. If
+ the instruction decoder sets this, it should always set it to
+ the same value in order to get reasonable looking output. */
+
+ info->bytes_per_line = 8;
+
+ /* In the next lines, we set two info variables control the way
+ objdump displays the raw data. For example, if bytes_per_line is
+ 8 and bytes_per_chunk is 4, the output will look like this:
+ 00: 00000000 00000000
+ with the chunks displayed according to "display_endian". */
+
+ if (info->section
+ && !(info->section->flags & SEC_CODE))
+ {
+ /* This is not a CODE section. */
+ switch (info->section->size)
+ {
+ case 1:
+ case 2:
+ case 4:
+ size = info->section->size;
+ break;
+ default:
+ size = (info->section->size & 0x01) ? 1 : 4;
+ break;
+ }
+ info->bytes_per_chunk = 1;
+ info->display_endian = info->endian;
+ }
+ else
+ {
+ size = 2;
+ info->bytes_per_chunk = 2;
+ info->display_endian = info->endian;
+ }
+
/* Read the insn into a host word. */
- status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ status = (*info->read_memory_func) (memaddr, buffer, size, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
if (info->section
&& !(info->section->flags & SEC_CODE))
{
- /* Sort of data section, just print a 32 bit number. */
- insnLen = 4;
- status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
- if (status != 0)
+ /* Data section. */
+ unsigned long data;
+
+ data = bfd_get_bits (buffer, size * 8,
+ info->display_endian == BFD_ENDIAN_BIG);
+ switch (size)
{
- (*info->memory_error_func) (status, memaddr + 2, info);
- return -1;
+ case 1:
+ (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
+ break;
+ case 2:
+ (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
+ break;
+ case 4:
+ (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
+ break;
+ default:
+ abort ();
}
- insn[0] = ARRANGE_ENDIAN (info, buffer);
- (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
- return insnLen;
+ return size;
}
- if ((((buffer[lowbyte] & 0xf8) > 0x38)
+ if ( (((buffer[lowbyte] & 0xf8) > 0x38)
&& ((buffer[lowbyte] & 0xf8) != 0x48))
|| ((info->mach == bfd_mach_arc_arcv2)
&& ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly. */
insn[0] = ARRANGE_ENDIAN (info, buffer);
}
- /* This variable may be set by the instruction decoder. It suggests
- the number of bytes objdump should display on a single line. If
- the instruction decoder sets this, it should always set it to
- the same value in order to get reasonable looking output. */
- info->bytes_per_line = 8;
-
- /* The next two variables control the way objdump displays the raw data.
- For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the
- output will look like this:
- 00: 00000000 00000000
- with the chunks displayed according to "display_endian". */
- info->bytes_per_chunk = 2;
- info->display_endian = info->endian;
-
/* Set some defaults for the insn info. */
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
/* Relocations. */
-#undef DEF
-#define DEF(NAME, EXC1, EXC2, RELOC1, RELOC2) \
- { #NAME, EXC1, EXC2, RELOC1, RELOC2}
-
const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
{
- DEF (sda, "ld", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
- DEF (sda, "st", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
- DEF (sda, "ldw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
- DEF (sda, "ldh", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
- DEF (sda, "stw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
- DEF (sda, "sth", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
+ { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+
+ /* Next two entries will cover the undefined behavior ldb/stb with
+ address scaling. */
+ { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+ { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
+
+ { "sda", "ld", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "st", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+ { "sda", "ldd", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "std", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
/* Short instructions. */
- DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD),
- DEF (sda, 0, F_NULL, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1),
- DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2),
- DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2),
-
- DEF (sda, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME),
- DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST),
-
- DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25H_PCREL,
- BFD_RELOC_ARC_S25H_PCREL_PLT),
- DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21H_PCREL,
- BFD_RELOC_ARC_S21H_PCREL_PLT),
- DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25W_PCREL,
- BFD_RELOC_ARC_S25W_PCREL_PLT),
- DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21W_PCREL,
- BFD_RELOC_ARC_S21W_PCREL_PLT),
-
- DEF (plt, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32),
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
+ { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
+
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
+ BFD_RELOC_ARC_S25H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
+ BFD_RELOC_ARC_S21H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
+ BFD_RELOC_ARC_S25W_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
+ BFD_RELOC_ARC_S21W_PCREL_PLT },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
};
const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
/* brk 00100101011011110000000000111111. */
-{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
/* brk_s 0111111111111111. */
-{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */
{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
/* clri c 00100111001011110000CCCCCC111111. */
{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
-/* clri 0 00100111001011110000111110111111. */
-{ "clri", 0x272F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { ZA }, { 0 }},
-
/* clri u6 00100111011011110000uuuuuu111111. */
{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+/* clri 00100111011011110000uuuuuu111111. */
+{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+
/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */
{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
{ "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* dsync 00100010011011110001RRRRRR111111. */
-{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* ei_s u10 010111uuuuuuuuuu. */
{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }},
{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
/* invld042e 00100RRRRR101110RRRRRRRRRRRRRRRR. */
-{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f0e 00100RRRRR101111RRRRRRRRRR00111R. */
-{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f12 00100RRRRR101111RRRRRRRRRR01001R. */
-{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f14 00100RRRRR101111RRRRRRRRRR0101RR. */
-{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f18 00100RRRRR101111RRRRRRRRRR011RRR. */
-{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f20 00100RRRRR101111RRRRRRRRRR10RRRR. */
-{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f30 00100RRRRR101111RRRRRRRRRR110RRR. */
-{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f38 00100RRRRR101111RRRRRRRRRR1110RR. */
-{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f3c 00100RRRRR101111RRRRRRRRRR11110R. */
-{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f3e 00100RRRRR101111RRRRRRRRRR111110. */
-{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f3f08 00100RRRRR101111R001RRRRRR111111. */
-{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f3f10 00100RRRRR101111R01RRRRRRR111111. */
-{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld042f3f20 00100RRRRR101111R1RRRRRRRR111111. */
-{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld0506 00101RRRRR00011RRRRRRRRRRRRRRRRR. */
-{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld050a 00101RRRRR00101RRRRRRRRRRRRRRRRR. */
-{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld050c 00101RRRRR00110RRRRRRRRRRRRRRRRR. */
-{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld051e 00101RRRRR01111RRRRRRRRRRRRRRRRR. */
-{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld0520 00101RRRRR100RRRRRRRRRRRRRRRRRRR. */
-{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld0528 00101RRRRR1010RRRRRRRRRRRRRRRRRR. */
-{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052c 00101RRRRR10110RRRRRRRRRRRRRRRRR. */
-{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052e 00101RRRRR101110RRRRRRRRRRRRRRRR. */
-{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f02 00101RRRRR101111RRRRRRRRRR00001R. */
-{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f04 00101RRRRR101111RRRRRRRRRR0001RR. */
-{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f14 00101RRRRR101111RRRRRRRRRR0101RR. */
-{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f18 00101RRRRR101111RRRRRRRRRR011RRR. */
-{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f20 00101RRRRR101111RRRRRRRRRR10RRRR. */
-{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f30 00101RRRRR101111RRRRRRRRRR110RRR. */
-{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f38 00101RRRRR101111RRRRRRRRRR1110RR. */
-{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f3c 00101RRRRR101111RRRRRRRRRR11110R. */
-{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f3e 00101RRRRR101111RRRRRRRRRR111110. */
-{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld052f3f00 00101RRRRR101111RRRRRRRRRR111111. */
-{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* invld07 00111RRRRRRRRRRRRRRRRRRRRRRRRRRR. */
-{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
+{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
/* j c 00100RRR001000000RRRCCCCCCRRRRRR. */
{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
/* nop 00100110010010100111000000000000. */
-{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* nop_s 0111100011100000. */
-{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */
{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* rtie 00100100011011110000000000111111. */
-{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
/* rtsc b,0 00110bbb01101111RBBB000000011010. */
{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, ZB }, { 0 }},
{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011. */
-{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_DI16 }},
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
/* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011. */
-{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_DI16 }},
+{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011. */
-{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_DI16 }},
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */
{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
/* seti limm 00100110001011110000111110111111. */
{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }},
+/* seti 00100110011011110000uuuuuu111111. */
+{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+
/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */
{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
/* swi 00100010011011110000000000111111. */
-{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
/* swi_s 0111101011100000. */
-{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
/* swi_s u6 01111uuuuuu11111. */
{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
/* sync 00100011011011110000000000111111. */
-{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* trap0 00100010011011110000000000111111. */
-{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { }, { 0 }},
+{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { 0 }, { 0 }},
/* trap_s u6 01111uuuuuu11110. */
{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
/* unimp_s 0111100111100000. */
-{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
/* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */
{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
projects / binutils-gdb.git / commitdiff