examples/de0_nano : add load cmd / change rst polarity

diff --git a/examples/de0_nano/Makefile b/examples/de0_nano/Makefile
index 3cc7ceaa4ea2311d95caf9906d700b5971305b3b..d537f1c4add2252cb94a0d71334ac4b419ba0e4a 100644 (file)
--- a/examples/de0_nano/Makefile
+++ b/examples/de0_nano/Makefile
@@ -9,6 +9,7 @@ build/de0_nano.qsf:
 
 build/de0_nano.map: build/de0_nano.qsf
        cp de0_nano.qpf build/de0_nano.qpf
+       cp de0_nano.sdc build/de0_nano.sdc      
        cd build && quartus_map de0_nano.qpf
        
 build/de0_nano.fit: build/de0_nano.map
@@ -20,6 +21,9 @@ build/de0_nano.asm: build/de0_nano.fit
 build/de0_nano.sta: build/de0_nano.asm
        cd build && quartus_sta de0_nano.qpf
 
+load:
+       cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;de0_nano.sof"
+
 clean:
        rm -rf build/*
 

diff --git a/examples/de0_nano/build.py b/examples/de0_nano/build.py
index 78618ee8488c8930a5acd76e162b99e38eeebf7f..76de5de1611d33c1c7958a29d60db098b95c971a 100644 (file)
--- a/examples/de0_nano/build.py
+++ b/examples/de0_nano/build.py
@@ -33,4 +33,4 @@ verilog_sources.append("build/de0_nano.v")
 
 # generate Quartus project file
 qsf_prj = get_qsf_prj()
-str2file("soc.qsf", qsf_prj + qsf_cst)
\ No newline at end of file
+str2file("de0_nano.qsf", qsf_prj + qsf_cst)
\ No newline at end of file

diff --git a/examples/de0_nano/constraints.py b/examples/de0_nano/constraints.py
index 4f3285cd442221b3367f02258c32e3fbd1e4c4d2..36f7d3630fda4d5fb51b65f90e9dbe453b4582a7 100644 (file)
--- a/examples/de0_nano/constraints.py
+++ b/examples/de0_nano/constraints.py
@@ -1,5 +1,5 @@
 class Constraints:
-       def __init__(self, in_clk, in_rst, spi2csr0, led0):
+       def __init__(self, in_clk, in_rst_n, spi2csr0, led0):
                self.constraints = []
                def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra,sch))
@@ -13,7 +13,7 @@ class Constraints:
                add(in_clk,  "R8")      # CLOCK_50
                
                # sys_rst
-               add(in_rst,  "J15")     # KEY[0]                        
+               add(in_rst_n,  "J15")   # KEY[0]                        
                                
                # spi2csr0 
                add(spi2csr0.spi_clk,  "A14")           #GPIO_2[0]
@@ -57,5 +57,7 @@ set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULA
 set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name DUTY_CYCLE 50 -section_id in_clk
+set_global_assignment -name FMAX_REQUIREMENT "50.0 MHz" -section_id in_clk
                        """
                return r

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index 5d5abf73cbbba8e24f6f4036b6b839f8a18f6645..c37e451d65f330f1bb868189d904625a7a716a65 100644 (file)
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -127,10 +127,14 @@ def get():
 
        # HouseKeeping
        in_clk = Signal()
+       in_rst_n = Signal()
        in_rst = Signal()
+       comb += [
+               in_rst.eq(~in_rst_n)
+       ]
        frag = autofragment.from_local()
        frag += Fragment(sync=sync,comb=comb)
-       cst = Constraints(in_clk, in_rst, spi2csr0, led0)
+       cst = Constraints(in_clk, in_rst_n, spi2csr0, led0)
        src_verilog, vns = verilog.convert(frag,
                cst.get_ios(),
                name="de0_nano",