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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 0a714e51d542920c3eff3acb6087d12a01fbed47..c4f507c81cee47f5c7a4dde9c183795a143d04c7 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -232,3 +232,19 @@ mask management, and transfer instructions between all the sane,
 which goes a long way towards explaining why there are twice as many
 Vector instructions in RISC-V as there are in the RV64GC base.
 
+The question then becomes: with all the duplication of arithmetic
+operations just to make the registers scalar or vector, why not
+leverage the *existing* Scalar ISA with some sort of "context"
+or prefix that augments its behaviour?
+
+Remarkably this is not a new idea.  Intel's x86 `REP` instruction
+gives the base concept, but in 1994 it was Peter Hsu, the designer
+of the MIPS R8000, who first came up with the idea of Vector
+prefixing.  Relying on a multi-issue Out-of-Order Execution Engine,
+the prefix would mark which of the registers were to be treated as
+Scalar and which as Vector, then perform a `REP`-like loop that
+jammed multiple scalar operations into the Multi-Issue Execution
+Engine.  The only reason that the team did not take this forward
+into a commercial product
+was because they could not work out how to cleanly do OoO
+multi-issue at the time.