altivec.md (altivec_vsumsws_be): Add define_expand.

gcc/ChangeLog:

2017-11-13  Carl Love  <cel@us.ibm.com>

	* config/rs6000/altivec.md (altivec_vsumsws_be): Add define_expand.

gcc/testsuite/ChangeLog:

2017-11-13 Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtin-vec-sums-be-int.c: New test file.

From-SVN: r254714

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b7ac84c44d700879373a50c716435c6be349bc15..13a60e8ed7d4676a108ea448edd6bf9465369a09 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-11-13  Carl Love  <cel@us.ibm.com>
+
+       * config/rs6000/altivec.md (altivec_vsumsws_be): Add define_expand.
+
 2017-11-13  Tom Tromey  <tom@tromey.com>
 
        * doc/cpp.texi (Variadic Macros): Document __VA_OPT__.

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 8eaa79783ff8b75efd6bf53389ccecdf406556c6..1ef98e3701220f6acdc6fd1ce93501d2709cb70a 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1079,6 +1079,7 @@ BU_ALTIVEC_2 (VSUM4SBS,         "vsum4sbs",       CONST,  altivec_vsum4sbs)
 BU_ALTIVEC_2 (VSUM4SHS,              "vsum4shs",       CONST,  altivec_vsum4shs)
 BU_ALTIVEC_2 (VSUM2SWS,              "vsum2sws",       CONST,  altivec_vsum2sws)
 BU_ALTIVEC_2 (VSUMSWS,       "vsumsws",        CONST,  altivec_vsumsws)
+BU_ALTIVEC_2 (VSUMSWS_BE,     "vsumsws_be",    CONST,  altivec_vsumsws_direct)
 BU_ALTIVEC_2 (VXOR,          "vxor",           CONST,  xorv4si3)
 BU_ALTIVEC_2 (COPYSIGN_V4SF,  "copysignfp",    CONST,  vector_copysignv4sf3)
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b1c2f3e05301a3b7aad233042e55995fe656fc5d..e5226149996a6e54c74a601be027650a11f4bfd2 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2017-11-13 Carl Love  <cel@us.ibm.com>
+
+       * gcc.target/powerpc/builtin-vec-sums-be-int.c: New test file.
+
 2017-11-13  Tom Tromey  <tom@tromey.com>
 
        * c-c++-common/cpp/va-opt-pedantic.c: New file.

diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c b/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c
new file mode 100644 (file)
index 0000000..b4dfd06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c
@@ -0,0 +1,16 @@
+/* Test for the __builtin_altivec_vsumsws_be() builtin.
+   It produces just the instruction vsumsws in LE and BE modes.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+test_vec_sums (vector signed int vsi2, vector signed int vsi3)
+{
+  return  __builtin_altivec_vsumsws_be (vsi2, vsi3);
+}
+
+/* { dg-final { scan-assembler-times "vsumsws" 1 } } */