Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
index e6ffd53db1b08b203b39cc98e1049bbb562c8ecb..0cf34adb34d0a3f25512365dbd22f96588ae004c 100644 (file)
--- a/examples/igloo2/example.pdc
+++ b/examples/igloo2/example.pdc
@@ -1 +1,8 @@
 # Add placement constraints here
+set_io clk  -pinname H16 -fixed yes -DIRECTION INPUT
+set_io SW1  -pinname H12 -fixed yes -DIRECTION INPUT
+set_io SW2  -pinname H13 -fixed yes -DIRECTION INPUT
+set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
+set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
+set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
+set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT

diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index c6ff941616339af6f321b831c9ade0bfef515a7b..f8b487316adc3d3106ad57afb5cef2bf45cd291f 100644 (file)
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -1 +1,2 @@
 # Add timing constraints here
+create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}]

diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 1a1967d5ae2e4292a2a833c648c52d32a496d257..b701c707d532a05e8fa602b5090562cff41af1aa 100644 (file)
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,23 +1,23 @@
 module example (
        input  clk,
-       input  EN,
+       input  SW1,
+       input  SW2,
        output LED1,
        output LED2,
        output LED3,
-       output LED4,
-       output LED5
+       output LED4
 );
 
-       localparam BITS = 5;
+       localparam BITS = 4;
        localparam LOG2DELAY = 22;
 
        reg [BITS+LOG2DELAY-1:0] counter = 0;
        reg [BITS-1:0] outcnt;
 
        always @(posedge clk) begin
-               counter <= counter + EN;
+               counter <= counter + SW1 + SW2 + 1;
                outcnt <= counter >> LOG2DELAY;
        end
 
-       assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+       assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
 endmodule

diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 6f7d4e24b93ac8e047d1ebfe6f2d203521c79497..abc94e479543033c65b784d80811782653ffcb59 100644 (file)
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -8,8 +8,8 @@ new_project \
     -block_mode 0 \
     -hdl "VERILOG" \
     -family IGLOO2 \
-    -die PA4MGL500 \
-    -package tq144 \
+    -die PA4MGL2500 \
+    -package vf256 \
     -speed -1
 
 import_files -hdl_source {netlist.vm}