gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
authorMarek Olšák <marek.olsak@amd.com>
Wed, 25 Oct 2017 23:50:44 +0000 (01:50 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 6 Nov 2017 18:09:12 +0000 (19:09 +0100)
18 files changed:
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/vc5/vc5_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h

index 376b95e89ddfe010939e41231536a9e153dbe47e..9f000596198fa9bdc1da588ce145730bf823457f 100644 (file)
@@ -414,6 +414,10 @@ The integer capabilities:
 * ``PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES``: Limit on combined shader
   output resources (images + buffers + fragment outputs). If 0 the state
   tracker works it out.
+* ``PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET``:
+  Whether pipe_vertex_buffer::buffer_offset is treated as signed. The u_vbuf
+  module needs this for optimal performance in workstation applications.
+
 
 .. _pipe_capf:
 
index 68973be5c7541a74b1325445d491f89a8ab5fbbb..bb789e69edc894afa6d86f7b7b10b95fc94d4e99 100644 (file)
@@ -267,6 +267,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
 
    /* Stream output. */
index 30b2dede118f79d2b424b59230e4e004ebf5978b..e5504b6b386cfc679d16d9979128018291bd9abb 100644 (file)
@@ -328,6 +328,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
        case PIPE_CAP_TILE_RASTER_ORDER:
        case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
                return 0;
 
        case PIPE_CAP_MAX_VIEWPORTS:
index 2a8853908dc103def990ba2d1b83fe98e2845948..26d0d804452a449ebdb948cb23f77ce7c018dd0b 100644 (file)
@@ -325,6 +325,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
 
    case PIPE_CAP_MAX_VIEWPORTS:
index fc11317687167516fb600bc42914f60ae1a6e22c..ee377dc61f83055438e5b4caa20857027fbba93c 100644 (file)
@@ -363,6 +363,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
    }
    /* should only get here on unhandled cases */
index 6ebce573ada52fbc05dfd120a4f6064190cfb9c0..81733335c48d130ddb8b0c9008aba88384003f7d 100644 (file)
@@ -227,6 +227,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 2066cf3f6e1e416b3faa51b5e5dbb49da40d7be6..90c19b7d2cd99b1cf2867986f87c06c9c0fdb5bf 100644 (file)
@@ -279,6 +279,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index d62a5552536296bd885e4e718d0962feb4659a91..45259c424d7f84bcafbf712d2e0704f4737b105e 100644 (file)
@@ -308,6 +308,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index a245c10748185cf48a6f22bc4f185d5a4093da64..72ba0ff84e3bf748898a59f4487b58c6d479324e 100644 (file)
@@ -249,6 +249,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
         case PIPE_CAP_TILE_RASTER_ORDER:
         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+        case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
             return 0;
 
         /* SWTCL-only features. */
index 3648f7d14eea20350a25562605079473cd8e39e8..e639d928830b648771925b277adbd84223dc502e 100644 (file)
@@ -405,6 +405,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
        case PIPE_CAP_TILE_RASTER_ORDER:
        case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
                return 0;
 
        case PIPE_CAP_DOUBLES:
index 875aff655ddc16530d6c26f5138e0e74a6222e6f..8212e340a5ce7f5f791ef30ffc6f25524968b000 100644 (file)
@@ -590,6 +590,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_POST_DEPTH_COVERAGE:
        case PIPE_CAP_TILE_RASTER_ORDER:
        case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
                return 0;
 
        case PIPE_CAP_NATIVE_FENCE_FD:
index c50d644b51de6ca4a2fef568683eb1e75abaa291..356ebf4e83311060e449e6b86f6cb06cc84cd362 100644 (file)
@@ -314,6 +314,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
       return 4;
index aede584610fe00eb662d057ea257b8eaea9b8bae..2a97ccb1886d051c863ab3094991d56948782716 100644 (file)
@@ -455,6 +455,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
    }
 
index 63d9f625e819fa8f8c56a110e4052d20eff4d97a..3f2433e65a94b1034a7e86d6ba64d80fe68e5726 100644 (file)
@@ -345,6 +345,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 9ac678d5b9774af9e31e231c2d23e26835236b2d..8128ee6f9d24939e4499696b5f75fdee9c9fa7c4 100644 (file)
@@ -287,6 +287,7 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_LOAD_CONSTBUF:
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
        case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
                 return 0;
 
                 /* Stream output. */
index e8bcef0d8fe6062d03420baed33503059917589d..cef40e70399269fc9ebc55ba06d44b06d05dc920 100644 (file)
@@ -111,6 +111,7 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_COMPUTE:
         case PIPE_CAP_DRAW_INDIRECT:
         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
+        case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
                 return 1;
 
         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
index 47e61aa81e99a562a5d243f73bb2f2635ad13099..56520156891da9886a75162dded6656a1d2f2f1c 100644 (file)
@@ -272,6 +272,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
       return 0;
    case PIPE_CAP_VENDOR_ID:
       return 0x1af4;
index 2db73c183d701e24bbbcac06760b3dcfe7bb4bc5..ddc951464b9130d82423e14c792c36c4f62736b0 100644 (file)
@@ -780,6 +780,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
    PIPE_CAP_TILE_RASTER_ORDER,
    PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
+   PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
 };
 
 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)