cpu-o3: fix store-release issuing

Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f7fb3fe3688bb9045fe486b3942450b8932b7c89..7383c6f9fe952ab776d13ee65d9e3b93b3489942 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,6 +1,6 @@
 
 /*
- * Copyright (c) 2010-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2017-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -753,6 +753,21 @@ LSQUnit<Impl>::writebackStores()
 
         DynInstPtr inst = storeWBIt->instruction();
         LSQRequest* req = storeWBIt->request();
+
+        // Process store conditionals or store release after all previous
+        // stores are completed
+        if ((req->mainRequest()->isLLSC() ||
+             req->mainRequest()->isRelease()) &&
+             (storeWBIt.idx() != storeQueue.head())) {
+            DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
+                "[sn:%lli] is %s%s and not head of the queue\n",
+                storeWBIt.idx(), inst->pcState(),
+                req->request()->getPaddr(), inst->seqNum,
+                req->mainRequest()->isLLSC() ? "SC" : "",
+                req->mainRequest()->isRelease() ? "/Release" : "");
+            break;
+        }
+
         storeWBIt->committed() = true;
 
         assert(!inst->memData);