(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index ff3b91851aab3ef3538488286decd7dd5c1b205d..4d74d1fff3bf2496efa2325e46d6634c887cc07d 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -15,7 +15,7 @@ Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]
 | 19   | RT  | RA   |     | XO[0:4]       | XO[5:9] |Rc| XL-Form |
 | 19   | RT  | RA   |imm  | imm //  vs ms | NNNNN   |Rc| setvl   |
 
-Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved abd must be zero.  Setting bit 22 causes an illegal exception.
+Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero.  Setting bit 22 causes an illegal exception.
 
 Note that VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1.  0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming nop.  If this is truly desired (nop behaviour) then setting VL and MVL to zero be done via the [[SV SPRs|sv/sprs]]