Fix code styling

diff --git a/gram/core/bankmachine.py b/gram/core/bankmachine.py
index 65f226dfeeb6866fe9a80ee23e6c327262f85183..ad289d664b3ae7838e29d9d80bf72ab10ef69b32 100644 (file)
--- a/gram/core/bankmachine.py
+++ b/gram/core/bankmachine.py
@@ -113,12 +113,9 @@ class BankMachine(Elaboratable):
             self.req.ready.eq(cmd_buffer_lookahead.sink.ready),
             cmd_buffer_lookahead.sink.payload.we.eq(self.req.we),
             cmd_buffer_lookahead.sink.payload.addr.eq(self.req.addr),
-
             cmd_buffer_lookahead.source.connect(cmd_buffer.sink),
-            cmd_buffer.source.ready.eq(
-                self.req.wdata_ready | self.req.rdata_valid),
-            self.req.lock.eq(cmd_buffer_lookahead.source.valid |
-                             cmd_buffer.source.valid),
+            cmd_buffer.source.ready.eq(self.req.wdata_ready | self.req.rdata_valid),
+            self.req.lock.eq(cmd_buffer_lookahead.source.valid | cmd_buffer.source.valid),
         ]
 
         m.submodules.lookahead_slicer = lookahead_slicer = _AddressSlicer(len(cmd_buffer_lookahead.source.addr),
@@ -154,13 +151,10 @@ class BankMachine(Elaboratable):
             m.d.comb += self.cmd.a.eq((auto_precharge << 10) | current_slicer.col)
 
         # tWTP (write-to-precharge) controller -----------------------------------------------------
-        write_latency = math.ceil(
-            self.settings.phy.cwl / self.settings.phy.nphases)
-        precharge_time = write_latency + self.settings.timing.tWR + \
-            self.settings.timing.tCCD  # AL=0
+        write_latency = math.ceil(self.settings.phy.cwl / self.settings.phy.nphases)
+        precharge_time = write_latency + self.settings.timing.tWR + self.settings.timing.tCCD  # AL=0
         m.submodules.twtpcon = twtpcon = tXXDController(precharge_time)
-        m.d.comb += twtpcon.valid.eq(self.cmd.valid &
-                                     self.cmd.ready & self.cmd.is_write)
+        m.d.comb += twtpcon.valid.eq(self.cmd.valid & self.cmd.ready & self.cmd.is_write)
 
         # tRC (activate-activate) controller -------------------------------------------------------
         m.submodules.trccon = trccon = tXXDController(self.settings.timing.tRC)

diff --git a/gram/core/controller.py b/gram/core/controller.py
index 4e36032f7730f7515ebf8b4c62b3c147e96e87b7..15aaaf744a17d986ef8af5ac0647a98f63dfed49 100644 (file)
--- a/gram/core/controller.py
+++ b/gram/core/controller.py
@@ -83,15 +83,12 @@ class gramController(Elaboratable):
         # Bank Machines ----------------------------------------------------------------------------
         bank_machines = []
         for n in range(nranks*nbanks):
-            bank_machine = BankMachine(n,
-                                       address_width=self.interface.address_width,
-                                       address_align=self._address_align,
-                                       nranks=nranks,
-                                       settings=self.settings)
+            bank_machine = BankMachine(n, address_width=self.interface.address_width,
+                address_align=self._address_align,
+                nranks=nranks, settings=self.settings)
             bank_machines.append(bank_machine)
             setattr(m.submodules, "bankmachine"+str(n), bank_machine)
-            m.d.comb += getattr(self.interface, "bank" +
-                                str(n)).connect(bank_machine.req)
+            m.d.comb += getattr(self.interface, "bank" + str(n)).connect(bank_machine.req)
 
         # Multiplexer ------------------------------------------------------------------------------
         m.submodules.multiplexer = Multiplexer(