(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4b392ee0076f8cdda6c13116b8f0bbb6fb26f94f..5aa83bdde9da20df4c9d005195264e32cdcfb838 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -587,8 +587,9 @@ cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputi
 has OpenCAPI Memory interfaces, and requires an OMI-to-DDR4/5 Bridge PHY
 to connect to standard DIMMs.
 
-Extra-V appears to be a remarkable research project that, by leveraging
-OpenCAPI, assuming that the map of edges in any given arbitrary data graph
+Extra-V appears to be a remarkable research project based on OpenCAPI that,
+by assuming that the map of edges (excluding the actual data)
+in any given arbitrary data graph
 could be kept by the main CPU in-memory, could distribute and delegate
 a limited-capability deterministic but most importantly *data-dependent*
 node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier).  A miniature processor