RISC-V: Add support for literal instruction arguments

This patch introduces support for arbitrary literal instruction
arguments, that are not encoded in the opcode.

A typical use case for this feature would be an instruction that
applies an implicit shift by a constant value on an immediate
(that is a real operand). With this patch it is possible to make
this shift visible in the dissasembly and support such artificial
parameter as part of the asssembly code.

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 00e4635de6e0bce6a03514294bed5c86d2f82a17..d9f63b1139859ba8332377e68c87446484af92bc 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1279,6 +1279,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 
            switch (*++oparg)
              {
+               case 'l': /* Literal.  */
+                 oparg += strcspn(oparg, ",") - 1;
+                 break;
                case 's': /* 'XsN@S' ... N-bit signed immediate at bit S.  */
                  goto use_imm;
                case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S.  */
@@ -3310,6 +3313,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 
                switch (*++oparg)
                  {
+                   case 'l': /* Literal.  */
+                     n = strcspn (++oparg, ",");
+                     if (strncmp (oparg, asarg, n))
+                       as_bad (_("unexpected literal (%s)"), asarg);
+                     oparg += n - 1;
+                     asarg += n;
+                     continue;
                    case 's': /* 'XsN@S' ... N-bit signed immediate at bit S.  */
                      sign = true;
                      goto parse_imm;

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2594e8182544832499de0cb338adb70793c628a8..f2d399260c1854d653f406e78e6fd79d42434985 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -570,6 +570,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 
            switch (*++oparg)
              {
+               case 'l': /* Literal.  */
+                 oparg++;
+                 while (*oparg && *oparg != ',')
+                   {
+                     print (info->stream, dis_style_text, "%c", *oparg);
+                     oparg++;
+                   }
+                 oparg--;
+                 break;
                case 's': /* 'XsN@S' ... N-bit signed immediate at bit S.  */
                  sign = true;
                  goto print_imm;