i965: Fix compiler warnings from hiz changes.

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 726d8d80af461c01177233350948efd1769a12cf..f9652df2d720b7338ea31e028e612a619d77963e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -330,8 +330,6 @@ static void emit_depthbuffer(struct brw_context *brw)
        * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
        *     [DevGT+]: This field must be set to TRUE.
        */
-      struct intel_region *region = stencil_mt->region;
-
       assert(intel->has_separate_stencil);
 
       BEGIN_BATCH(len);

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index d7a3dae571a18d7151dbe041b738496b9b4ebd01..8a383f5ed127844187070080db396d194cd29907 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -69,8 +69,6 @@ static void emit_depthbuffer(struct brw_context *brw)
       if (stencil_mt == NULL) {
         dw1 |= (BRW_SURFACE_NULL << 29);
       } else {
-        struct intel_region *region = stencil_mt->region;
-
         /* _NEW_STENCIL: enable stencil buffer writes */
         dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);