from m5.objects import *
from Benchmarks import *
from FullO3Config import *
-from Util import *
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
-def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None):
+def makeLinuxAlphaSystem(mem_mode, mdesc):
self = LinuxAlphaSystem()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
- self.cpu = cpu
self.mem_mode = mem_mode
- connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
- for each_cpu in makeList(self.cpu):
- each_cpu.itb = AlphaITB()
- each_cpu.dtb = AlphaDTB()
- self.cpu.clock = '2GHz'
self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
self.kernel = binary('vmlinux')
self.pal = binary('ts_osfpal')
m5.AddToPath('../common')
from FSConfig import *
from SysPaths import *
-from Util import *
from Benchmarks import *
parser = optparse.OptionParser()
bm = Benchmarks[options.benchmark]
if len(bm) == 2:
- root = makeDualRoot(makeLinuxAlphaSystem(cpu, mem_mode, bm[0]),
- makeLinuxAlphaSystem(cpu2, mem_mode, bm[1]))
-
+ s1 = makeLinuxAlphaSystem(mem_mode, bm[0])
+ s2 = makeLinuxAlphaSystem(mem_mode, bm[1])
+ cpu.connectMemPorts(s1.membus)
+ cpu2.connectMemPorts(s2.membus)
+ root = makeDualRoot(s1, s2)
elif len(bm) == 1:
root = Root(clock = '1THz',
- system = makeLinuxAlphaSystem(cpu, mem_mode, bm[0]))
+ system = makeLinuxAlphaSystem(mem_mode, bm[0]))
+ cpu.connectMemPorts(root.system.membus)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
from m5 import build_env
from m5.config import *
+from AlphaTLB import AlphaDTB, AlphaITB
+from Bus import Bus
class BaseCPU(SimObject):
type = 'BaseCPU'
system = Param.System(Parent.any, "system object")
if build_env['FULL_SYSTEM']:
- dtb = Param.AlphaDTB("Data TLB")
- itb = Param.AlphaITB("Instruction TLB")
+ dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
+ itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
cpu_id = Param.Int(-1, "CPU identifier")
else:
workload = VectorParam.Process("processes to run")
"defer registration with system (for sampling)")
clock = Param.Clock(Parent.clock, "clock speed")
+
+ _mem_ports = []
+
+ def connectMemPorts(self, bus):
+ for p in self._mem_ports:
+ exec('self.%s = bus.port' % p)
+
+ def addPrivateSplitL1Caches(self, ic, dc):
+ assert(len(self._mem_ports) == 2)
+ self.icache = ic
+ self.dcache = dc
+ self.icache_port = ic.cpu_side
+ self.dcache_port = dc.cpu_side
+ self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+
+ def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
+ self.addPrivateSplitL1Caches(ic, dc)
+ self.toL2Bus = Bus()
+ self.connectMemPorts(self.toL2Bus)
+ self.l2cache = l2c
+ self.l2cache.cpu_side = toL2Bus.port
+ self._mem_ports = ['l2cache.mem_side']
cachePorts = Param.Unsigned("Cache Ports")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
+ _mem_ports = ['icache_port', 'dcache_port']
decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
--- /dev/null
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.cpu.workload = LiveProcess(file = binpath('hello'))
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=fuPool mem
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.mem
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.workload
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.workload
+mem=system.cpu.mem
+checker=null
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 47245 # Number of BTB hits
+global.BPredUnit.BTBLookups 62226 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted
+global.BPredUnit.lookups 72853 # Number of BP lookups
+global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target.
+host_inst_rate 90438 # Simulator instruction rate (inst/s)
+host_mem_usage 148172 # Number of bytes of host memory used
+host_seconds 5.53 # Real time elapsed on the host
+host_tick_rate 35958 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500002 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 198813 # Number of ticks simulated
+system.cpu.commit.COM:branches 61160 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 189916
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 37455 1972.19%
+ 1 50343 2650.80%
+ 2 29014 1527.73%
+ 3 12786 673.25%
+ 4 19808 1042.99%
+ 5 2516 132.48%
+ 6 10075 530.50%
+ 7 3395 178.76%
+ 8 24524 1291.31%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 518948 # Number of instructions committed
+system.cpu.commit.COM:loads 131376 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 189772 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 500002 # Number of Instructions Simulated
+system.cpu.committedInsts_total 500002 # Number of Instructions Simulated
+system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads
+system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched
+system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 198814
+system.cpu.fetch.rateDist.min_value 0
+ 0 85330 4291.95%
+ 1 3737 187.96%
+ 2 9626 484.17%
+ 3 11018 554.19%
+ 4 8626 433.87%
+ 5 19021 956.72%
+ 6 27490 1382.70%
+ 7 6216 312.65%
+ 8 27750 1395.78%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.iew.EXEC:branches 65998 # Number of branches executed
+system.cpu.iew.EXEC:insts 534582 # Number of executed instructions
+system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 21827 # number of nop insts executed
+system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate
+system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 60185 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 413743 # num instructions consuming a value
+system.cpu.iew.WB:count 532886 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 308589 # num instructions producing a value
+system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle
+system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:(null).samples 0
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+system.cpu.iq.IQ:residence:(null).max_value 0
+system.cpu.iq.IQ:residence:(null).end_dist
+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntAlu.samples 0
+system.cpu.iq.IQ:residence:IntAlu.min_value 0
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+system.cpu.iq.IQ:residence:IntAlu.max_value 0
+system.cpu.iq.IQ:residence:IntAlu.end_dist
+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntMult.samples 0
+system.cpu.iq.IQ:residence:IntMult.min_value 0
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+system.cpu.iq.IQ:residence:IntMult.max_value 0
+system.cpu.iq.IQ:residence:IntMult.end_dist
+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntDiv.samples 0
+system.cpu.iq.IQ:residence:IntDiv.min_value 0
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+system.cpu.iq.IQ:residence:IntDiv.max_value 0
+system.cpu.iq.IQ:residence:IntDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatAdd.samples 0
+system.cpu.iq.IQ:residence:FloatAdd.min_value 0
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+system.cpu.iq.IQ:residence:FloatAdd.max_value 0
+system.cpu.iq.IQ:residence:FloatAdd.end_dist
+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCmp.samples 0
+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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+system.cpu.iq.IQ:residence:FloatCmp.max_value 0
+system.cpu.iq.IQ:residence:FloatCmp.end_dist
+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCvt.samples 0
+system.cpu.iq.IQ:residence:FloatCvt.min_value 0
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+system.cpu.iq.IQ:residence:FloatCvt.max_value 0
+system.cpu.iq.IQ:residence:FloatCvt.end_dist
+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatMult.samples 0
+system.cpu.iq.IQ:residence:FloatMult.min_value 0
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+system.cpu.iq.IQ:residence:FloatMult.max_value 0
+system.cpu.iq.IQ:residence:FloatMult.end_dist
+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatDiv.samples 0
+system.cpu.iq.IQ:residence:FloatDiv.min_value 0
+ 0 0
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+system.cpu.iq.IQ:residence:FloatDiv.max_value 0
+system.cpu.iq.IQ:residence:FloatDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatSqrt.samples 0
+system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
+ 0 0
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+system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemRead.samples 0
+system.cpu.iq.IQ:residence:MemRead.min_value 0
+ 0 0
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+system.cpu.iq.IQ:residence:MemRead.max_value 0
+system.cpu.iq.IQ:residence:MemRead.end_dist
+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemWrite.samples 0
+system.cpu.iq.IQ:residence:MemWrite.min_value 0
+ 0 0
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+system.cpu.iq.IQ:residence:MemWrite.max_value 0
+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IprAccess.samples 0
+system.cpu.iq.IQ:residence:IprAccess.min_value 0
+ 0 0
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+system.cpu.iq.IQ:residence:IprAccess.max_value 0
+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:InstPrefetch.samples 0
+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
+ 0 0
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+system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
+system.cpu.iq.IQ:residence:InstPrefetch.end_dist
+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:(null)_delay.samples 0
+system.cpu.iq.ISSUE:(null)_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:(null)_delay.max_value 0
+system.cpu.iq.ISSUE:(null)_delay.end_dist
+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
+system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
+system.cpu.iq.ISSUE:IntMult_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
+system.cpu.iq.ISSUE:IntMult_delay.end_dist
+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
+system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
+system.cpu.iq.ISSUE:IntDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
+system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
+system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
+system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 336144 62.06% # Type of FU issued
+ IntMult 10 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 13 0.00% # Type of FU issued
+ FloatCmp 3 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 2 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 144008 26.59% # Type of FU issued
+ MemWrite 61441 11.34% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 6229 59.96% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 2497 24.04% # attempts to use FU when none available
+ MemWrite 1663 16.01% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 198814
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 27333 1374.80%
+ 1 36906 1856.31%
+ 2 35716 1796.45%
+ 3 28916 1454.42%
+ 4 31868 1602.91%
+ 5 13027 655.24%
+ 6 21677 1090.32%
+ 7 3102 156.03%
+ 8 269 13.53%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate
+system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.numCycles 198814 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:11 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed
+Exiting @ tick 198813 because a thread reached the max instruction count
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=mem
+clock=1
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.mem
+simulate_stalls=false
+system=system
+width=1
+workload=system.workload
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.cpu.mem
+system=system
+workload=system.workload
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1310554 # Simulator instruction rate (inst/s)
+host_mem_usage 147620 # Number of bytes of host memory used
+host_seconds 0.38 # Real time elapsed on the host
+host_tick_rate 1308843 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500000 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 499999 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 500000 # number of cpu cycles simulated
+system.cpu.num_insts 500000 # Number of instructions executed
+system.cpu.num_refs 182204 # Number of memory references
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:11 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/atomic tests/test1/run.py
+Exiting @ tick 499999 because a thread reached the max instruction count
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=mem
+clock=1
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.mem
+system=system
+workload=system.workload
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.cpu.mem
+system=system
+workload=system.workload
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 781730 # Simulator instruction rate (inst/s)
+host_mem_usage 147616 # Number of bytes of host memory used
+host_seconds 0.64 # Real time elapsed on the host
+host_tick_rate 1063244 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500000 # Number of instructions simulated
+sim_seconds 0.000001 # Number of seconds simulated
+sim_ticks 680774 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 0 # number of cpu cycles simulated
+system.cpu.num_insts 500000 # Number of instructions executed
+system.cpu.num_refs 182203 # Number of memory references
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:14 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/timing tests/test1/run.py --timing
+Exiting @ tick 680774 because a thread reached the max instruction count
--- /dev/null
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.cpu.workload = EioProcess(file = binpath('anagram-vshort.eio.gz'))
+root.system.cpu.max_insts_any_thread = 500000
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu physmem workload
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=fuPool mem
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-mem=system.cpu.mem
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.workload
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.mem]
-type=Bus
-bus_id=0
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-
-[system.workload]
-type=EioProcess
-chkpt=
-file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
-output=cout
-system=system
-
-[trace]
-bufsize=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-// range not specified
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.workload]
-type=EioProcess
-file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
-chkpt=
-output=cout
-system=system
-
-[system.cpu.mem]
-type=Bus
-bus_id=0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.workload
-mem=system.cpu.mem
-checker=null
-max_insts_any_thread=500000
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[trace]
-flags=
-start=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 47245 # Number of BTB hits
-global.BPredUnit.BTBLookups 62226 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted
-global.BPredUnit.lookups 72853 # Number of BP lookups
-global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target.
-host_inst_rate 90438 # Simulator instruction rate (inst/s)
-host_mem_usage 148172 # Number of bytes of host memory used
-host_seconds 5.53 # Real time elapsed on the host
-host_tick_rate 35958 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 500002 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 198813 # Number of ticks simulated
-system.cpu.commit.COM:branches 61160 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 189916
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 37455 1972.19%
- 1 50343 2650.80%
- 2 29014 1527.73%
- 3 12786 673.25%
- 4 19808 1042.99%
- 5 2516 132.48%
- 6 10075 530.50%
- 7 3395 178.76%
- 8 24524 1291.31%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 518948 # Number of instructions committed
-system.cpu.commit.COM:loads 131376 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 189772 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 500002 # Number of Instructions Simulated
-system.cpu.committedInsts_total 500002 # Number of Instructions Simulated
-system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads
-system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched
-system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 198814
-system.cpu.fetch.rateDist.min_value 0
- 0 85330 4291.95%
- 1 3737 187.96%
- 2 9626 484.17%
- 3 11018 554.19%
- 4 8626 433.87%
- 5 19021 956.72%
- 6 27490 1382.70%
- 7 6216 312.65%
- 8 27750 1395.78%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.iew.EXEC:branches 65998 # Number of branches executed
-system.cpu.iew.EXEC:insts 534582 # Number of executed instructions
-system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 21827 # number of nop insts executed
-system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate
-system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 60185 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 413743 # num instructions consuming a value
-system.cpu.iew.WB:count 532886 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 308589 # num instructions producing a value
-system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle
-system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 84 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 86 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 32 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemRead.samples 0
-system.cpu.iq.IQ:residence:MemRead.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 14 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 84 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 84 0
- 86 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 336144 62.06% # Type of FU issued
- IntMult 10 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 13 0.00% # Type of FU issued
- FloatCmp 3 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 2 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 144008 26.59% # Type of FU issued
- MemWrite 61441 11.34% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 6229 59.96% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 2497 24.04% # attempts to use FU when none available
- MemWrite 1663 16.01% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 198814
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 27333 1374.80%
- 1 36906 1856.31%
- 2 35716 1796.45%
- 3 28916 1454.42%
- 4 31868 1602.91%
- 5 13027 655.24%
- 6 21677 1090.32%
- 7 3102 156.03%
- 8 269 13.53%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate
-system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.numCycles 198814 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
-system.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-
-gzip: stdout: Broken pipe
+++ /dev/null
-main dictionary has 1245 entries
-49508 bytes wasted
->M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 27 2006 17:25:03
-M5 started Thu Jul 27 17:25:11 2006
-M5 executing on zamp.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed
-Exiting @ tick 198813 because a thread reached the max instruction count
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu physmem workload
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=mem
-clock=1
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-mem=system.cpu.mem
-simulate_stalls=false
-system=system
-width=1
-workload=system.workload
-
-[system.cpu.mem]
-type=Bus
-bus_id=0
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-
-[system.workload]
-type=EioProcess
-chkpt=
-file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
-output=cout
-system=system
-
-[trace]
-bufsize=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-// range not specified
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.workload]
-type=EioProcess
-file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
-chkpt=
-output=cout
-system=system
-
-[system.cpu.mem]
-type=Bus
-bus_id=0
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=500000
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-mem=system.cpu.mem
-system=system
-workload=system.workload
-clock=1
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[trace]
-flags=
-start=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1310554 # Simulator instruction rate (inst/s)
-host_mem_usage 147620 # Number of bytes of host memory used
-host_seconds 0.38 # Real time elapsed on the host
-host_tick_rate 1308843 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 500000 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 499999 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 500000 # number of cpu cycles simulated
-system.cpu.num_insts 500000 # Number of instructions executed
-system.cpu.num_refs 182204 # Number of memory references
-system.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
-
-gzip: stdout: Broken pipe
+++ /dev/null
-main dictionary has 1245 entries
-49508 bytes wasted
->M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 27 2006 17:25:03
-M5 started Thu Jul 27 17:25:11 2006
-M5 executing on zamp.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/atomic tests/test1/run.py
-Exiting @ tick 499999 because a thread reached the max instruction count
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu physmem workload
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=mem
-clock=1
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-mem=system.cpu.mem
-system=system
-workload=system.workload
-
-[system.cpu.mem]
-type=Bus
-bus_id=0
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-
-[system.workload]
-type=EioProcess
-chkpt=
-file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
-output=cout
-system=system
-
-[trace]
-bufsize=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-// range not specified
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.workload]
-type=EioProcess
-file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
-chkpt=
-output=cout
-system=system
-
-[system.cpu.mem]
-type=Bus
-bus_id=0
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=500000
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-mem=system.cpu.mem
-system=system
-workload=system.workload
-clock=1
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[trace]
-flags=
-start=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 781730 # Simulator instruction rate (inst/s)
-host_mem_usage 147616 # Number of bytes of host memory used
-host_seconds 0.64 # Real time elapsed on the host
-host_tick_rate 1063244 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 500000 # Number of instructions simulated
-sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 680774 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 0 # number of cpu cycles simulated
-system.cpu.num_insts 500000 # Number of instructions executed
-system.cpu.num_refs 182203 # Number of memory references
-system.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
-
-gzip: stdout: Broken pipe
+++ /dev/null
-main dictionary has 1245 entries
-49508 bytes wasted
->M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 27 2006 17:25:03
-M5 started Thu Jul 27 17:25:14 2006
-M5 executing on zamp.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/timing tests/test1/run.py --timing
-Exiting @ tick 680774 because a thread reached the max instruction count
+++ /dev/null
-root.system.cpu.workload = EioProcess(file = tests_root + '/test-progs/anagram/bin/anagram-vshort.eio.gz')
-root.system.cpu.max_insts_any_thread = 500000
# find path to directory containing this file
tests_root = os.path.dirname(__file__)
+test_progs = os.path.join(tests_root, 'test-progs')
+
+# generate path to binary file
+def binpath(app, file=None):
+ # executable has same name as app unless specified otherwise
+ if not file:
+ file = app
+ return os.path.join(test_progs, app, 'bin', isa, opsys, file)
# build configuration
execfile(os.path.join(tests_root, config + '.py'))
# set default maxtick... script can override
-maxtick = 1000000
+# -1 means run forever
+maxtick = -1
# tweak configuration for specific test
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-system.cpu.icache_port = system.membus.port
-system.cpu.dcache_port = system.membus.port
+system.cpu.connectMemPorts(system.membus)
root = Root(system = system)
-
tgts_per_mshr = 5
cpu = TimingSimpleCPU()
-cpu.icache = MyCache(size = '128kB')
-cpu.dcache = MyCache(size = '256kB')
-cpu.l2cache = MyCache(size = '2MB')
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+ MyCache(size = '2MB'))
-cpu.icache_port = cpu.icache.cpu_side
-cpu.dcache_port = cpu.dcache.cpu_side
+system = System(cpu = cpu,
+ physmem = PhysicalMemory(),
+ membus = Bus())
+system.physmem.port = system.membus.port
+cpu.connectMemPorts(system.membus)
-root = makeSESystem(cpu)
+root = Root(system = system)
projects / gem5.git / commitdiff