Fix broken timing constraints

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 25bfa2853b134db5b8e2f85e13b14c02e5f87ec8..128035d203e17a88cc09e7faf417fd7629c4e6f7 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -421,12 +421,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             m.d.async_ff += o.eq(i)
 
         if async_ff_sync._edge == "pos":
-            m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
+            m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i)
         else:
-            m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
+            m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
             async_ff_sync.o.eq(flops[-1])
         ]