(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index e6b4e4aa5732a0717dd702abc30eeac157b517c1..180ff8c17e7aed19cb8ea7111c03d6e4d7999bf6 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -410,8 +410,10 @@ If addition to another Matrix is also required then it is only three
 instructions. Not only that, but because the "Schedule" is an abstract
 concept separated from the mathematical operation, there is no reason
 why Matrix Multiplication Schedules may not be applied to Integer
-Mul-and-Accumulate, Galois Field Mul-and-Accumulate, or Logical
-AND-and-OR.  The flexibility is not only enormous, but the compactness
+Mul-and-Accumulate, Galois Field Mul-and-Accumulate, Logical
+AND-and-OR, or any other future instruction such as Complex-Number
+Multiply-and-Accumulate that a future version of the Power ISA might
+support.  The flexibility is not only enormous, but the compactness
 unprecedented.  RADIX2 in-place DCT Triple-loop Schedules may be created in
 around 11 instructions. The only other processors well-known to have
 this type of compact capability are both VLIW DSPs: TI's TMS320 Series