soc/cores/gpio: add GPIO Tristate

diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py
index 2102889827f9add8b64dc9e595c213541be6d032..a2541072f7efa2007872e9b2a24d9824dfb360e4 100644 (file)
--- a/litex/soc/cores/gpio.py
+++ b/litex/soc/cores/gpio.py
@@ -29,3 +29,17 @@ class GPIOInOut(Module):
 
     def get_csrs(self):
         return self.gpio_in.get_csrs() + self.gpio_out.get_csrs()
+
+# GPIO Tristate ------------------------------------------------------------------------------------
+
+class GPIOTristate(Module, AutoCSR):
+    def __init__(self, pads):
+        self._oe  = CSRStorage(len(pads))
+        self._in  = CSRStatus(len(pads))
+        self._out = CSRStorage(len(pads))
+
+        t = TSTriple(len(pads))
+        self.specials += t.get_tristate(pads)
+        self.comb += t.oe.eq(self._oe.storage)
+        self.comb += t.o.eq(self._out.storage)
+        self.specials += MultiReg(t.i, self._in.status)