def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic,
with_bandwidth=False):
assert(phy_settings.nphases == len(dfi.phases))
+ self.phy_settings = phy_settings
# Command choosing
requests = [bm.cmd for bm in bank_machines]
def do_finalize(self):
if self.with_bandwidth:
- self.submodules.bandwidth = Bandwidth(self.choose_req.cmd)
+ data_width = self.phy_settings.dfi_databits*self.phy_settings.nphases
+ self.submodules.bandwidth = Bandwidth(self.choose_req.cmd, data_width)
from migen.bank.description import *
class Bandwidth(Module, AutoCSR):
- def __init__(self, cmd, period_bits=24):
+ def __init__(self, cmd, data_width, period_bits=24):
self._update = CSR()
self._nreads = CSRStatus(period_bits)
self._nwrites = CSRStatus(period_bits)
+ self._data_width = CSRStatus(bits_for(data_width), reset=data_width)
###
#include <console.h>
#include <system.h>
+static unsigned int log2(unsigned int v)
+{
+ unsigned int r;
+ r = 0;
+ while(v>>=1) r++;
+ return r;
+}
+
static void membw_service(void)
{
static int last_event;
unsigned long long int nr, nw;
unsigned long long int f;
unsigned int rdb, wrb;
+ unsigned int dw;
if(elapsed(&last_event, identifier_frequency_read())) {
sdram_controller_bandwidth_update_write(1);
nr = sdram_controller_bandwidth_nreads_read();
nw = sdram_controller_bandwidth_nwrites_read();
f = identifier_frequency_read();
- rdb = (nr*f >> (24 - 7))/1000000ULL;
- wrb = (nw*f >> (24 - 7))/1000000ULL;
+ dw = sdram_controller_bandwidth_data_width_read();
+ rdb = (nr*f >> (24 - log2(dw)))/1000000ULL;
+ wrb = (nw*f >> (24 - log2(dw)))/1000000ULL;
printf("read:%5dMbps write:%5dMbps all:%5dMbps\n", rdb, wrb, rdb + wrb);
}
}