max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
pid=100
ppid=99
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
opClass=IntAlu
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
bus_id=0
clock=1000
width=64
+responder_set=false
[trace]
flags=
global.BPredUnit.condPredicted 1570 # Number of conditional branches predicted
global.BPredUnit.lookups 5322 # Number of BP lookups
global.BPredUnit.usedRAS 2820 # Number of times the RAS was used to get a target.
-host_inst_rate 1288 # Simulator instruction rate (inst/s)
-host_mem_usage 180572 # Number of bytes of host memory used
-host_seconds 4.37 # Real time elapsed on the host
-host_tick_rate 322418 # Simulator tick rate (ticks/s)
+host_inst_rate 9098 # Simulator instruction rate (inst/s)
+host_mem_usage 180112 # Number of bytes of host memory used
+host_seconds 0.62 # Real time elapsed on the host
+host_tick_rate 2277354 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 144 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 3819 # Number of loads inserted to the mem dependence unit.
system.cpu.dcache.overall_accesses 2409 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 5958.666667 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 6120.796512 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1986 # number of overall hits
system.cpu.dcache.overall_miss_latency 2520516 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.175592 # miss rate for overall accesses
system.cpu.icache.overall_accesses 6541 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5110.042601 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4297.762058 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 6095 # number of overall hits
system.cpu.icache.overall_miss_latency 2279079 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.068185 # miss rate for overall accesses
system.cpu.ipc_total 0.003993 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 13960 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
-(null) 2 0.01% # Type of FU issued
-IntAlu 8277 59.29% # Type of FU issued
-IntMult 1 0.01% # Type of FU issued
-IntDiv 0 0.00% # Type of FU issued
-FloatAdd 2 0.01% # Type of FU issued
-FloatCmp 0 0.00% # Type of FU issued
-FloatCvt 0 0.00% # Type of FU issued
-FloatMult 0 0.00% # Type of FU issued
-FloatDiv 0 0.00% # Type of FU issued
-FloatSqrt 0 0.00% # Type of FU issued
-MemRead 3509 25.14% # Type of FU issued
-MemWrite 2169 15.54% # Type of FU issued
-IprAccess 0 0.00% # Type of FU issued
-InstPrefetch 0 0.00% # Type of FU issued
+ (null) 2 0.01% # Type of FU issued
+ IntAlu 8277 59.29% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.01% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 3509 25.14% # Type of FU issued
+ MemWrite 2169 15.54% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006662 # FU busy rate (busy events/executed inst)
system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4537.301455 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2307.006237 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2182442 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995859 # miss rate for overall accesses
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
All Rights Reserved
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:07:55 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:43 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Exiting @ tick 1408131 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
progress_interval=0
simulate_stalls=false
system=system
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.physmem
system=system
cpu_id=0
workload=system.cpu.workload
---------- Begin Simulation Statistics ----------
-host_inst_rate 172802 # Simulator instruction rate (inst/s)
-host_mem_usage 148116 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 170614 # Simulator tick rate (ticks/s)
+host_inst_rate 684709 # Simulator instruction rate (inst/s)
+host_mem_usage 148256 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 650634 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
warn: Entering event queue @ 0. Starting simulation...
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
All Rights Reserved
-M5 compiled Oct 8 2006 14:00:39
-M5 started Sun Oct 8 14:00:50 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:43 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Exiting @ tick 5641 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
progress_interval=0
system=system
workload=system.cpu.workload
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
bus_id=0
clock=1000
width=64
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+responder_set=false
[system.cpu.workload]
type=LiveProcess
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.cpu.dcache
system=system
cpu_id=0
workload=system.cpu.workload
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.icache]
type=BaseCache
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
---------- Begin Simulation Statistics ----------
-host_inst_rate 8293 # Simulator instruction rate (inst/s)
-host_mem_usage 179892 # Number of bytes of host memory used
-host_seconds 0.68 # Real time elapsed on the host
-host_tick_rate 2595779 # Simulator tick rate (ticks/s)
+host_inst_rate 179790 # Simulator instruction rate (inst/s)
+host_mem_usage 179436 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 55533187 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1626 # number of overall hits
system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5366 # number of overall hits
system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
warn: Entering event queue @ 0. Starting simulation...
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
All Rights Reserved
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:08:16 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:44 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Exiting @ tick 1767066 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
pid=100
ppid=99
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
opClass=IntAlu
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
bus_id=0
clock=1000
width=64
+responder_set=false
[trace]
flags=
global.BPredUnit.condPredicted 451 # Number of conditional branches predicted
global.BPredUnit.lookups 891 # Number of BP lookups
global.BPredUnit.usedRAS 172 # Number of times the RAS was used to get a target.
-host_inst_rate 1447 # Simulator instruction rate (inst/s)
-host_mem_usage 180084 # Number of bytes of host memory used
-host_seconds 1.65 # Real time elapsed on the host
-host_tick_rate 455868 # Simulator tick rate (ticks/s)
+host_inst_rate 20134 # Simulator instruction rate (inst/s)
+host_mem_usage 179640 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
+host_tick_rate 6326998 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 8 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 784 # Number of loads inserted to the mem dependence unit.
system.cpu.dcache.overall_accesses 856 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 6991.981481 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 694 # number of overall hits
system.cpu.dcache.overall_miss_latency 1132701 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.189252 # miss rate for overall accesses
system.cpu.icache.overall_accesses 814 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4971.589641 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 563 # number of overall hits
system.cpu.icache.overall_miss_latency 1247869 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.308354 # miss rate for overall accesses
system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3500 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
-(null) 0 0.00% # Type of FU issued
-IntAlu 2460 70.29% # Type of FU issued
-IntMult 1 0.03% # Type of FU issued
-IntDiv 0 0.00% # Type of FU issued
-FloatAdd 0 0.00% # Type of FU issued
-FloatCmp 0 0.00% # Type of FU issued
-FloatCvt 0 0.00% # Type of FU issued
-FloatMult 0 0.00% # Type of FU issued
-FloatDiv 0 0.00% # Type of FU issued
-FloatSqrt 0 0.00% # Type of FU issued
-MemRead 695 19.86% # Type of FU issued
-MemWrite 344 9.83% # Type of FU issued
-IprAccess 0 0.00% # Type of FU issued
-InstPrefetch 0 0.00% # Type of FU issued
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 2460 70.29% # Type of FU issued
+ IntMult 1 0.03% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 0 0.00% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 695 19.86% # Type of FU issued
+ MemWrite 344 9.83% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.010000 # FU busy rate (busy events/executed inst)
system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4622.063197 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1243335 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
warn: cycle 109049: fault (page_table_fault) detected @ PC 0x000000
warn: cycle 109050: fault (page_table_fault) detected @ PC 0x000000
warn: cycle 109051: fault (page_table_fault) detected @ PC 0x000000
All Rights Reserved
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:08:37 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:50 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Exiting @ tick 752027 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
progress_interval=0
simulate_stalls=false
system=system
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.physmem
system=system
cpu_id=0
workload=system.cpu.workload
---------- Begin Simulation Statistics ----------
-host_inst_rate 60702 # Simulator instruction rate (inst/s)
-host_mem_usage 147692 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 60102 # Simulator tick rate (ticks/s)
+host_inst_rate 480164 # Simulator instruction rate (inst/s)
+host_mem_usage 147928 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 437596 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
warn: Entering event queue @ 0. Starting simulation...
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
All Rights Reserved
-M5 compiled Oct 8 2006 14:00:39
-M5 started Sun Oct 8 14:00:54 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:50 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Exiting @ tick 2577 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
progress_interval=0
system=system
workload=system.cpu.workload
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
bus_id=0
clock=1000
width=64
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+responder_set=false
[system.cpu.workload]
type=LiveProcess
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.cpu.dcache
system=system
cpu_id=0
workload=system.cpu.workload
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.icache]
type=BaseCache
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
---------- Begin Simulation Statistics ----------
-host_inst_rate 7429 # Simulator instruction rate (inst/s)
-host_mem_usage 179540 # Number of bytes of host memory used
-host_seconds 0.35 # Real time elapsed on the host
-host_tick_rate 2820365 # Simulator tick rate (ticks/s)
+host_inst_rate 153015 # Simulator instruction rate (inst/s)
+host_mem_usage 179088 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 56749783 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 627 # number of overall hits
system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2416 # number of overall hits
system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
warn: Entering event queue @ 0. Starting simulation...
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
All Rights Reserved
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:08:56 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:51 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Exiting @ tick 980012 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
bus_id=0
clock=1000
width=64
+responder_set=false
[system.cpu.workload0]
type=LiveProcess
pid=100
ppid=99
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
opClass=IntAlu
numThreads=1
activity=0
workload=system.cpu.workload0 system.cpu.workload1
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
bus_id=0
clock=1000
width=64
+responder_set=false
[trace]
flags=
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 1308 # Number of BTB hits
-global.BPredUnit.BTBLookups 6837 # Number of BTB lookups
+global.BPredUnit.BTBHits 1309 # Number of BTB hits
+global.BPredUnit.BTBLookups 6835 # Number of BTB lookups
global.BPredUnit.RASInCorrect 164 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1235 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 4603 # Number of conditional branches predicted
-global.BPredUnit.lookups 12596 # Number of BP lookups
-global.BPredUnit.usedRAS 5739 # Number of times the RAS was used to get a target.
-host_inst_rate 945 # Simulator instruction rate (inst/s)
-host_mem_usage 181580 # Number of bytes of host memory used
-host_seconds 11.90 # Real time elapsed on the host
-host_tick_rate 187981 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads.
+global.BPredUnit.condIncorrect 1233 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 4602 # Number of conditional branches predicted
+global.BPredUnit.lookups 12593 # Number of BP lookups
+global.BPredUnit.usedRAS 5738 # Number of times the RAS was used to get a target.
+host_inst_rate 9412 # Simulator instruction rate (inst/s)
+host_mem_usage 181120 # Number of bytes of host memory used
+host_seconds 1.20 # Real time elapsed on the host
+host_tick_rate 1873386 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 0 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 52 # Number of conflicting stores.
memdepunit.memDep.conflictingStores 3 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 6560 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 3600 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 6549 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 3592 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 5837 # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 2389 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 11247 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
-sim_ticks 2237162 # Number of ticks simulated
+sim_ticks 2239163 # Number of ticks simulated
system.cpu.commit.COM:branches 1724 # Number of branches committed
system.cpu.commit.COM:branches_0 862 # Number of branches committed
system.cpu.commit.COM:branches_1 862 # Number of branches committed
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 189229
+system.cpu.commit.COM:committed_per_cycle.samples 185440
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 183654 9705.38%
- 1 3073 162.40%
- 2 1213 64.10%
- 3 492 26.00%
- 4 307 16.22%
- 5 181 9.57%
- 6 120 6.34%
- 7 59 3.12%
- 8 130 6.87%
+ 0 179865 9699.36%
+ 1 3074 165.77%
+ 2 1213 65.41%
+ 3 492 26.53%
+ 4 305 16.45%
+ 5 181 9.76%
+ 6 120 6.47%
+ 7 60 3.24%
+ 8 130 7.01%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 980 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 978 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 31727 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 31695 # The number of squashed insts skipped by commit
system.cpu.committedInsts_0 5624 # Number of Instructions Simulated
system.cpu.committedInsts_1 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
-system.cpu.cpi_0 397.788407 # CPI: Cycles Per Instruction
-system.cpu.cpi_1 397.859150 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 198.911888 # CPI: Total CPI of All Threads
+system.cpu.cpi_0 398.144203 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 398.215010 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 199.089802 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 3208 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses_0 3208 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10081.356250 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency_0 10081.356250 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10477.810000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10477.810000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2888 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 2888 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3226034 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 3226034 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.099751 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate_0 0.099751 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 320 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 320 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 120 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2095562 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 2095562 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 10071.492212 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency_0 10071.492212 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10492.815000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10492.815000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2887 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 2887 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3232949 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 3232949 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.100062 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate_0 0.100062 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 321 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 321 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 121 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2098563 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 2098563 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.062344 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.062344 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 200 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3977 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 3606.011765 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.575145 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 11.572254 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 85 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 3977 # number of cycles access was blocked
system.cpu.dcache.demand_accesses 4832 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_0 4832 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 7905.902056 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 7905.902056 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 7904.705314 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 7904.705314 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9355.303468 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 9355.303468 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9363.976879 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 9363.976879 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4005 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 4005 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 4004 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 4004 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 6538181 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 6538181 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 6545096 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 6545096 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.171151 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.171151 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_1 no value # miss rate for demand accesses
-system.cpu.dcache.demand_misses 827 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 827 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate 0.171358 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.171358 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
+system.cpu.dcache.demand_misses 828 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 828 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 481 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 481 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 482 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3236935 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 3236935 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 3239936 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 3239936 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.071606 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_0 0.071606 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 346 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_0 346 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_accesses 4832 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_0 4832 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 7905.902056 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 7905.902056 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 7904.705314 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 7904.705314 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9355.303468 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 9355.303468 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9363.976879 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 9363.976879 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4005 # number of overall hits
-system.cpu.dcache.overall_hits_0 4005 # number of overall hits
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 4004 # number of overall hits
+system.cpu.dcache.overall_hits_0 4004 # number of overall hits
system.cpu.dcache.overall_hits_1 0 # number of overall hits
-system.cpu.dcache.overall_miss_latency 6538181 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 6538181 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 6545096 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 6545096 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.171151 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.171151 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_1 no value # miss rate for overall accesses
-system.cpu.dcache.overall_misses 827 # number of overall misses
-system.cpu.dcache.overall_misses_0 827 # number of overall misses
+system.cpu.dcache.overall_miss_rate 0.171358 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.171358 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
+system.cpu.dcache.overall_misses 828 # number of overall misses
+system.cpu.dcache.overall_misses_0 828 # number of overall misses
system.cpu.dcache.overall_misses_1 0 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 481 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 481 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits 482 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 482 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3236935 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 3236935 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 3239936 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 3239936 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.071606 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_0 0.071606 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 346 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_0 346 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 198.595005 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4005 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 198.721819 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4004 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 101864 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 96221 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 264 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 379 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 73628 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 257376 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 12701 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 6044 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:DecodedInsts 73578 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 255461 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 12691 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 6036 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 680 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 340 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 12596 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 13043 # Number of cache lines fetched
-system.cpu.fetch.Cycles 28220 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1653 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 84650 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 4944 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.066558 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 52829 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.decode.DECODE:UnblockCycles 337 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 12593 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13036 # Number of cache lines fetched
+system.cpu.fetch.Cycles 28204 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1652 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 84597 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 4941 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.067901 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 52822 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 7047 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.447294 # Number of inst fetches per cycle
+system.cpu.fetch.rate 0.456147 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 189249
+system.cpu.fetch.rateDist.samples 185460
system.cpu.fetch.rateDist.min_value 0
- 0 174064 9197.62%
- 1 369 19.50%
- 2 570 30.12%
- 3 3356 177.33%
- 4 1799 95.06%
- 5 1035 54.69%
- 6 675 35.67%
- 7 2396 126.61%
- 8 4985 263.41%
+ 0 170284 9181.71%
+ 1 368 19.84%
+ 2 571 30.79%
+ 3 3355 180.90%
+ 4 1795 96.79%
+ 5 1036 55.86%
+ 6 675 36.40%
+ 7 2396 129.19%
+ 8 4980 268.52%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 13041 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses_0 13041 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 7799.181319 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency_0 7799.181319 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 7166.106518 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7166.106518 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 12131 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits_0 12131 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 7097255 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency_0 7097255 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.069780 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate_0 0.069780 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 910 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses_0 910 # number of ReadReq misses
+system.cpu.icache.ReadReq_accesses 13034 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses_0 13034 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7812.430296 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency_0 7812.430296 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 7184.680952 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7184.680952 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12123 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits_0 12123 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 7117124 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency_0 7117124 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.069894 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate_0 0.069894 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 911 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses_0 911 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 281 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits_0 281 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4507481 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency_0 4507481 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.048232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate_0 0.048232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 629 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses_0 629 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency 4526349 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency_0 4526349 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.048335 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate_0 0.048335 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 630 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses_0 630 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 5755.187500 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 19.286169 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles_no_targets 5755.250000 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 19.242857 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 16 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 92083 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 92084 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 13041 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_0 13041 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 13034 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_0 13034 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 7799.181319 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_0 7799.181319 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency 7812.430296 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_0 7812.430296 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 7166.106518 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_0 7166.106518 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 7184.680952 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_0 7184.680952 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 12131 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_0 12131 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 12123 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_0 12123 # number of demand (read+write) hits
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 7097255 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_0 7097255 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 7117124 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_0 7117124 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.069780 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_0 0.069780 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_1 no value # miss rate for demand accesses
-system.cpu.icache.demand_misses 910 # number of demand (read+write) misses
-system.cpu.icache.demand_misses_0 910 # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate 0.069894 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_0 0.069894 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
+system.cpu.icache.demand_misses 911 # number of demand (read+write) misses
+system.cpu.icache.demand_misses_0 911 # number of demand (read+write) misses
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 281 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_0 281 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4507481 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_0 4507481 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 4526349 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_0 4526349 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.048232 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_0 0.048232 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 629 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_0 629 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_rate 0.048335 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_0 0.048335 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 630 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_0 630 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 13041 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_0 13041 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 13034 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_0 13034 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 7799.181319 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_0 7799.181319 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 7812.430296 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_0 7812.430296 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 7166.106518 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_0 7166.106518 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 7184.680952 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_0 7184.680952 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 12131 # number of overall hits
-system.cpu.icache.overall_hits_0 12131 # number of overall hits
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 12123 # number of overall hits
+system.cpu.icache.overall_hits_0 12123 # number of overall hits
system.cpu.icache.overall_hits_1 0 # number of overall hits
-system.cpu.icache.overall_miss_latency 7097255 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_0 7097255 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 7117124 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_0 7117124 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.069780 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_0 0.069780 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_1 no value # miss rate for overall accesses
-system.cpu.icache.overall_misses 910 # number of overall misses
-system.cpu.icache.overall_misses_0 910 # number of overall misses
+system.cpu.icache.overall_miss_rate 0.069894 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_0 0.069894 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
+system.cpu.icache.overall_misses 911 # number of overall misses
+system.cpu.icache.overall_misses_0 911 # number of overall misses
system.cpu.icache.overall_misses_1 0 # number of overall misses
system.cpu.icache.overall_mshr_hits 281 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_0 281 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4507481 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_0 4507481 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 4526349 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_0 4526349 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.048232 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_0 0.048232 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 629 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_0 629 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_rate 0.048335 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_0 0.048335 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 630 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_0 630 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 6 # number of replacements
system.cpu.icache.replacements_0 6 # number of replacements
system.cpu.icache.replacements_1 0 # number of replacements
-system.cpu.icache.sampled_refs 629 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 630 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 289.520052 # Cycle average of tags in use
-system.cpu.icache.total_refs 12131 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 289.830640 # Cycle average of tags in use
+system.cpu.icache.total_refs 12123 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.writebacks_0 0 # number of writebacks
system.cpu.icache.writebacks_1 0 # number of writebacks
-system.cpu.idleCycles 2047914 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 4335 # Number of branches executed
-system.cpu.iew.EXEC:branches_0 2743 # Number of branches executed
-system.cpu.iew.EXEC:branches_1 1592 # Number of branches executed
+system.cpu.idleCycles 2053704 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 4333 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 2744 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 1589 # Number of branches executed
system.cpu.iew.EXEC:nop 76 # number of nop insts executed
system.cpu.iew.EXEC:nop_0 38 # number of nop insts executed
system.cpu.iew.EXEC:nop_1 38 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.146521 # Inst execution rate
-system.cpu.iew.EXEC:refs 11792 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_0 7324 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_1 4468 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 3821 # Number of stores executed
-system.cpu.iew.EXEC:stores_0 2506 # Number of stores executed
+system.cpu.iew.EXEC:rate 0.149461 # Inst execution rate
+system.cpu.iew.EXEC:refs 11794 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 7333 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 4461 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 3822 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 2507 # Number of stores executed
system.cpu.iew.EXEC:stores_1 1315 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 12302 # num instructions consuming a value
-system.cpu.iew.WB:consumers_0 6628 # num instructions consuming a value
-system.cpu.iew.WB:consumers_1 5674 # num instructions consuming a value
-system.cpu.iew.WB:count 22631 # cumulative count of insts written-back
-system.cpu.iew.WB:count_0 12849 # cumulative count of insts written-back
-system.cpu.iew.WB:count_1 9782 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.818810 # average fanout of values written-back
-system.cpu.iew.WB:fanout_0 0.828908 # average fanout of values written-back
-system.cpu.iew.WB:fanout_1 0.807014 # average fanout of values written-back
+system.cpu.iew.WB:consumers 12300 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 6629 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 5671 # num instructions consuming a value
+system.cpu.iew.WB:count 22619 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 12848 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 9771 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.818780 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.828933 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.806912 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 10073 # num instructions producing a value
-system.cpu.iew.WB:producers_0 5494 # num instructions producing a value
-system.cpu.iew.WB:producers_1 4579 # num instructions producing a value
-system.cpu.iew.WB:rate 0.119583 # insts written-back per cycle
-system.cpu.iew.WB:rate_0 0.067895 # insts written-back per cycle
-system.cpu.iew.WB:rate_1 0.051689 # insts written-back per cycle
-system.cpu.iew.WB:sent 22783 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_0 12935 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_1 9848 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 1057 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 60428 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 10160 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 10071 # num instructions producing a value
+system.cpu.iew.WB:producers_0 5495 # num instructions producing a value
+system.cpu.iew.WB:producers_1 4576 # num instructions producing a value
+system.cpu.iew.WB:rate 0.121962 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.069276 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.052685 # insts written-back per cycle
+system.cpu.iew.WB:sent 22770 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 12934 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 9836 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 1054 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 56608 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 10141 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 5995 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 5984 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 8226 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 42995 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 7971 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_0 4818 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_1 3153 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1093 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 27729 # Number of executed instructions
+system.cpu.iew.iewDispatchedInsts 42965 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 7972 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 4826 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 3146 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 27719 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 6044 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 109 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 6036 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 111 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 3147 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.cacheBlocked 3148 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 62 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 39 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 5581 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 5570 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 5025 # Number of stores squashed
system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.1.cacheBlocked 1500 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.1.memOrderViolation 34 # Number of memory ordering violations
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 2621 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedLoads 2613 # Number of loads squashed
system.cpu.iew.lsq.thread.1.squashedStores 1577 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 74 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 830 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.memOrderViolationEvents 73 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 827 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0 0.002514 # IPC: Instructions Per Cycle
-system.cpu.ipc_1 0.002513 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.005027 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 16810 # Type of FU issued
+system.cpu.ipc_0 0.002512 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.002511 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.005023 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 16815 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
-(null) 2 0.01% # Type of FU issued
-IntAlu 9156 54.47% # Type of FU issued
-IntMult 1 0.01% # Type of FU issued
-IntDiv 0 0.00% # Type of FU issued
-FloatAdd 2 0.01% # Type of FU issued
-FloatCmp 0 0.00% # Type of FU issued
-FloatCvt 0 0.00% # Type of FU issued
-FloatMult 0 0.00% # Type of FU issued
-FloatDiv 0 0.00% # Type of FU issued
-FloatSqrt 0 0.00% # Type of FU issued
-MemRead 5111 30.40% # Type of FU issued
-MemWrite 2538 15.10% # Type of FU issued
-IprAccess 0 0.00% # Type of FU issued
-InstPrefetch 0 0.00% # Type of FU issued
+ (null) 2 0.01% # Type of FU issued
+ IntAlu 9152 54.43% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.01% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 5119 30.44% # Type of FU issued
+ MemWrite 2539 15.10% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:FU_type_1 12012 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1 11998 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
(null) 2 0.02% # Type of FU issued
- IntAlu 7390 61.52% # Type of FU issued
+ IntAlu 7386 61.56% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 3275 27.26% # Type of FU issued
- MemWrite 1342 11.17% # Type of FU issued
+ MemRead 3265 27.21% # Type of FU issued
+ MemWrite 1342 11.19% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
-system.cpu.iq.ISSUE:FU_type 28822 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type 28813 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
(null) 4 0.01% # Type of FU issued
- IntAlu 16546 57.41% # Type of FU issued
+ IntAlu 16538 57.40% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 4 0.01% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 8386 29.10% # Type of FU issued
- MemWrite 3880 13.46% # Type of FU issued
+ MemRead 8384 29.10% # Type of FU issued
+ MemWrite 3881 13.47% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 154 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt 150 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_cnt_0 76 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_1 78 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.005343 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_0 0.002637 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_1 0.002706 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt_1 74 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005206 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.002638 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.002568 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 3 1.95% # attempts to use FU when none available
+ IntAlu 3 2.00% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 86 55.84% # attempts to use FU when none available
- MemWrite 65 42.21% # attempts to use FU when none available
+ MemRead 84 56.00% # attempts to use FU when none available
+ MemWrite 63 42.00% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 189249
+system.cpu.iq.ISSUE:issued_per_cycle.samples 185460
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 174743 9233.50%
- 1 7200 380.45%
- 2 2967 156.78%
- 3 2563 135.43%
- 4 1137 60.08%
- 5 450 23.78%
- 6 138 7.29%
- 7 35 1.85%
- 8 16 0.85%
+ 0 170959 9218.11%
+ 1 7202 388.33%
+ 2 2947 158.90%
+ 3 2569 138.52%
+ 4 1155 62.28%
+ 5 444 23.94%
+ 6 134 7.23%
+ 7 34 1.83%
+ 8 16 0.86%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.152297 # Inst issue rate
-system.cpu.iq.iqInstsAdded 42876 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 28822 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.155360 # Inst issue rate
+system.cpu.iq.iqInstsAdded 42846 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 28813 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 30249 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 220 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 30225 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 210 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 25020 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 975 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses_0 975 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 6774.326824 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency_0 6774.326824 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3621.391572 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3621.391572 # average ReadReq mshr miss latency
+system.cpu.iq.iqSquashedOperandsExamined 24996 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses_0 976 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 6784.690965 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency_0 6784.690965 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3622.808008 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3622.808008 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 6591420 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency_0 6591420 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997949 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate_0 0.997949 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 973 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses_0 973 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 3523614 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3523614 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997949 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997949 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 973 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses_0 973 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 6608289 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency_0 6608289 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997951 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate_0 0.997951 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 974 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses_0 974 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 3528615 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3528615 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997951 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997951 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 974 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses_0 974 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002055 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002053 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 975 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0 975 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 976 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0 976 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 6774.326824 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_0 6774.326824 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 6784.690965 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_0 6784.690965 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 3621.391572 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3621.391572 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 3622.808008 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3622.808008 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6591420 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_0 6591420 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 6608289 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_0 6608289 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997949 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_0 0.997949 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_1 no value # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 973 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses_0 973 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_rate 0.997951 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_0 0.997951 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 974 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses_0 974 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 3523614 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_0 3523614 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 3528615 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_0 3528615 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997949 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_0 0.997949 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 973 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses_0 973 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_rate 0.997951 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_0 0.997951 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 974 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses_0 974 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 975 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0 975 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 976 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0 976 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 6774.326824 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_0 6774.326824 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 6784.690965 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_0 6784.690965 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 3621.391572 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3621.391572 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 3622.808008 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3622.808008 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_hits_0 2 # number of overall hits
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6591420 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_0 6591420 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 6608289 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_0 6608289 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997949 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_0 0.997949 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_1 no value # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 973 # number of overall misses
-system.cpu.l2cache.overall_misses_0 973 # number of overall misses
+system.cpu.l2cache.overall_miss_rate 0.997951 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_0 0.997951 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 974 # number of overall misses
+system.cpu.l2cache.overall_misses_0 974 # number of overall misses
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3523614 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_0 3523614 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 3528615 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_0 3528615 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997949 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_0 0.997949 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 973 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses_0 973 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_rate 0.997951 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_0 0.997951 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 974 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses_0 974 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.replacements_0 0 # number of replacements
system.cpu.l2cache.replacements_1 0 # number of replacements
-system.cpu.l2cache.sampled_refs 973 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 974 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 489.175621 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 489.614756 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.writebacks_0 0 # number of writebacks
system.cpu.l2cache.writebacks_1 0 # number of writebacks
-system.cpu.numCycles 189249 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 77071 # Number of cycles rename is blocking
+system.cpu.numCycles 185460 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 73308 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 22 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 258812 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2912 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 26 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 78724 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 64105 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 44626 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 11563 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 6044 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 2613 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 36524 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 22222 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IQFullEvents 20 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 256900 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2907 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 29 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 78661 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 64047 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 44573 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 11548 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 6036 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2611 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 36471 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 20343 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 52 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 5371 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 5370 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
-system.cpu.timesIdled 686 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 688 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
warn: Default fetch doesn't update it's state from a functional call.
-warn: Found outstanding miss on an non-update probe
warn: Default fetch doesn't update it's state from a functional call.
All Rights Reserved
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:09:16 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:57 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
-Exiting @ tick 2237162 because target called exit()
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
+Exiting @ tick 2239163 because target called exit()
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
profile=0
progress_interval=0
simulate_stalls=false
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
profile=0
progress_interval=0
simulate_stalls=false
[system.iobus]
type=Bus
+children=responder
bus_id=0
clock=2
+responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+
[system.membus]
type=Bus
+children=responder
bus_id=1
clock=2
+responder_set=false
width=64
+default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+pio=system.membus.default
+
[system.physmem]
type=PhysicalMemory
file=
bus_id=1
clock=2
width=64
+responder_set=false
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+itb=system.cpu0.itb
+dtb=system.cpu0.dtb
+profile=0
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu0
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[system.bridge]
type=Bridge
driveID=master
delay=2000
-[system.cpu0.itb]
-type=AlphaITB
-size=48
-
-[system.cpu0.dtb]
-type=AlphaDTB
-size=64
-
-[system.cpu0]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-mem=system.physmem
-system=system
-cpu_id=0
-itb=system.cpu0.itb
-dtb=system.cpu0.dtb
-profile=0
-clock=1
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
[system.cpu1.itb]
type=AlphaITB
size=48
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.physmem
system=system
cpu_id=1
itb=system.cpu1.itb
function_trace_start=0
simulate_stalls=false
-[system.intrctrl]
-type=IntrControl
-cpu=system.cpu0
-
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
system=system
disk=system.simple_disk.disk
-[system.tsunami]
-type=Tsunami
-system=system
-intrctrl=system.intrctrl
-
[system.tsunami.fake_uart1]
type=IsaFake
pio_addr=8804615848696
bus_id=0
clock=2
width=64
+responder_set=true
+
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[trace]
flags=
---------- Begin Simulation Statistics ----------
-host_inst_rate 1270607 # Simulator instruction rate (inst/s)
-host_mem_usage 197696 # Number of bytes of host memory used
-host_seconds 51.09 # Real time elapsed on the host
-host_tick_rate 72782461 # Simulator tick rate (ticks/s)
+host_inst_rate 1289947 # Simulator instruction rate (inst/s)
+host_mem_usage 199348 # Number of bytes of host memory used
+host_seconds 50.32 # Real time elapsed on the host
+host_tick_rate 73890229 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 64909600 # Number of instructions simulated
sim_seconds 1.859078 # Number of seconds simulated
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
-Listening for console connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 195723: Trying to launch CPU number 1!
All Rights Reserved
-M5 compiled Oct 8 2006 21:57:24
-M5 started Sun Oct 8 21:58:13 2006
-M5 executing on zed.eecs.umich.edu
+M5 compiled Nov 5 2006 19:41:29
+M5 started Sun Nov 5 20:03:49 2006
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Exiting @ tick 3718155709 because m5_exit instruction encountered
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
profile=0
progress_interval=0
simulate_stalls=false
[system.iobus]
type=Bus
+children=responder
bus_id=0
clock=2
+responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+
[system.membus]
type=Bus
+children=responder
bus_id=1
clock=2
+responder_set=false
width=64
+default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+pio=system.membus.default
+
[system.physmem]
type=PhysicalMemory
file=
bus_id=1
clock=2
width=64
+responder_set=false
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+itb=system.cpu.itb
+dtb=system.cpu.dtb
+profile=0
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[system.bridge]
type=Bridge
driveID=master
delay=2000
-[system.cpu.itb]
-type=AlphaITB
-size=48
-
-[system.cpu.dtb]
-type=AlphaDTB
-size=64
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-mem=system.physmem
-system=system
-cpu_id=0
-itb=system.cpu.itb
-dtb=system.cpu.dtb
-profile=0
-clock=1
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[system.intrctrl]
-type=IntrControl
-cpu=system.cpu
-
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
system=system
disk=system.simple_disk.disk
-[system.tsunami]
-type=Tsunami
-system=system
-intrctrl=system.intrctrl
-
[system.tsunami.fake_uart1]
type=IsaFake
pio_addr=8804615848696
bus_id=0
clock=2
width=64
+responder_set=true
+
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[trace]
flags=
---------- Begin Simulation Statistics ----------
-host_inst_rate 1389289 # Simulator instruction rate (inst/s)
-host_mem_usage 197652 # Number of bytes of host memory used
-host_seconds 44.48 # Real time elapsed on the host
-host_tick_rate 81712411 # Simulator tick rate (ticks/s)
+host_inst_rate 1313531 # Simulator instruction rate (inst/s)
+host_mem_usage 199136 # Number of bytes of host memory used
+host_seconds 47.04 # Real time elapsed on the host
+host_tick_rate 77256650 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 61788439 # Number of instructions simulated
sim_seconds 1.817090 # Number of seconds simulated
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
Listening for console connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
All Rights Reserved
-M5 compiled Oct 8 2006 21:57:24
-M5 started Sun Oct 8 21:57:28 2006
-M5 executing on zed.eecs.umich.edu
+M5 compiled Nov 5 2006 19:41:29
+M5 started Sun Nov 5 20:03:49 2006
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Exiting @ tick 3634179176 because m5_exit instruction encountered
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
profile=0
progress_interval=0
system=system
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
profile=0
progress_interval=0
system=system
[system.iobus]
type=Bus
+children=responder
bus_id=0
clock=2
+responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+
[system.membus]
type=Bus
+children=responder
bus_id=1
clock=2
+responder_set=false
width=64
+default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+pio=system.membus.default
+
[system.physmem]
type=PhysicalMemory
file=
bus_id=1
clock=2
width=64
+responder_set=false
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+itb=system.cpu0.itb
+dtb=system.cpu0.dtb
+profile=0
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu0
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[system.bridge]
type=Bridge
driveID=master
delay=2000
-[system.cpu0.itb]
-type=AlphaITB
-size=48
-
-[system.cpu0.dtb]
-type=AlphaDTB
-size=64
-
-[system.cpu0]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-mem=system.physmem
-system=system
-cpu_id=0
-itb=system.cpu0.itb
-dtb=system.cpu0.dtb
-profile=0
-clock=1
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
[system.cpu1.itb]
type=AlphaITB
size=48
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.physmem
system=system
cpu_id=1
itb=system.cpu1.itb
function_trace_start=0
// simulate_stalls not specified
-[system.intrctrl]
-type=IntrControl
-cpu=system.cpu0
-
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
system=system
disk=system.simple_disk.disk
-[system.tsunami]
-type=Tsunami
-system=system
-intrctrl=system.intrctrl
-
[system.tsunami.fake_uart1]
type=IsaFake
pio_addr=8804615848696
bus_id=0
clock=2
width=64
+responder_set=true
+
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[trace]
flags=
\runix_boot_mem ends at FFFFFC0000078000
\rk_argc = 0
\rjumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
-\rCallbackFixup 0 18000, t7=FFFFFC000070C000
\rEntering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+\rCallbackFixup 0 18000, t7=FFFFFC000070C000
\rLinux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
\rBooting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
\rMajor Options: SMP LEGACY_START VERBOSE_MCHECK
---------- Begin Simulation Statistics ----------
-host_inst_rate 255147 # Simulator instruction rate (inst/s)
-host_mem_usage 198260 # Number of bytes of host memory used
-host_seconds 260.00 # Real time elapsed on the host
-host_tick_rate 14365182 # Simulator tick rate (ticks/s)
+host_inst_rate 341883 # Simulator instruction rate (inst/s)
+host_mem_usage 198856 # Number of bytes of host memory used
+host_seconds 195.81 # Real time elapsed on the host
+host_tick_rate 20274403 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
-sim_insts 66337257 # Number of instructions simulated
-sim_seconds 1.867449 # Number of seconds simulated
-sim_ticks 3734898877 # Number of ticks simulated
-system.cpu0.dtb.accesses 828318 # DTB accesses
-system.cpu0.dtb.acv 315 # DTB access violations
-system.cpu0.dtb.hits 13264910 # DTB hits
-system.cpu0.dtb.misses 7094 # DTB misses
-system.cpu0.dtb.read_accesses 572336 # DTB read accesses
-system.cpu0.dtb.read_acv 200 # DTB read access violations
-system.cpu0.dtb.read_hits 8201218 # DTB read hits
-system.cpu0.dtb.read_misses 6394 # DTB read misses
-system.cpu0.dtb.write_accesses 255982 # DTB write accesses
+sim_insts 66945470 # Number of instructions simulated
+sim_seconds 1.985009 # Number of seconds simulated
+sim_ticks 3970017178 # Number of ticks simulated
+system.cpu0.dtb.accesses 1003481 # DTB accesses
+system.cpu0.dtb.acv 289 # DTB access violations
+system.cpu0.dtb.hits 13332675 # DTB hits
+system.cpu0.dtb.misses 8437 # DTB misses
+system.cpu0.dtb.read_accesses 695694 # DTB read accesses
+system.cpu0.dtb.read_acv 174 # DTB read access violations
+system.cpu0.dtb.read_hits 8285791 # DTB read hits
+system.cpu0.dtb.read_misses 7640 # DTB read misses
+system.cpu0.dtb.write_accesses 307787 # DTB write accesses
system.cpu0.dtb.write_acv 115 # DTB write access violations
-system.cpu0.dtb.write_hits 5063692 # DTB write hits
-system.cpu0.dtb.write_misses 700 # DTB write misses
-system.cpu0.idle_fraction 0.982517 # Percentage of idle cycles
-system.cpu0.itb.accesses 1888651 # ITB accesses
-system.cpu0.itb.acv 166 # ITB acv
-system.cpu0.itb.hits 1885318 # ITB hits
-system.cpu0.itb.misses 3333 # ITB misses
-system.cpu0.kern.callpal 146863 # number of callpals executed
+system.cpu0.dtb.write_hits 5046884 # DTB write hits
+system.cpu0.dtb.write_misses 797 # DTB write misses
+system.cpu0.idle_fraction 0.928150 # Percentage of idle cycles
+system.cpu0.itb.accesses 2398201 # ITB accesses
+system.cpu0.itb.acv 143 # ITB acv
+system.cpu0.itb.hits 2394377 # ITB hits
+system.cpu0.itb.misses 3824 # ITB misses
+system.cpu0.kern.callpal 144637 # number of callpals executed
system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir 506 0.34% 0.35% # number of callpals executed
-system.cpu0.kern.callpal_wrmces 1 0.00% 0.35% # number of callpals executed
-system.cpu0.kern.callpal_wrfen 1 0.00% 0.35% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.35% # number of callpals executed
-system.cpu0.kern.callpal_swpctx 2962 2.02% 2.36% # number of callpals executed
-system.cpu0.kern.callpal_tbi 47 0.03% 2.40% # number of callpals executed
-system.cpu0.kern.callpal_wrent 7 0.00% 2.40% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 132443 90.18% 92.58% # number of callpals executed
-system.cpu0.kern.callpal_rdps 6236 4.25% 96.83% # number of callpals executed
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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+system.cpu0.kern.inst.hwrei 159963 # number of hwrei instructions executed
system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed
system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed
-system.cpu0.kern.inst.quiesce 6637 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 139203 # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0 55744 40.05% 40.05% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21 245 0.18% 40.22% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22 1904 1.37% 41.59% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30 410 0.29% 41.88% # number of times we switched to this ipl
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-system.cpu0.kern.ipl_good 112527 # number of times we switched to this ipl from a different ipl
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-system.cpu0.kern.ipl_good_21 245 0.22% 49.26% # number of times we switched to this ipl from a different ipl
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-system.cpu0.kern.ipl_ticks_0 3696326531 98.98% 98.98% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21 53683 0.00% 98.98% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22 224672 0.01% 98.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30 128286 0.00% 98.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 37645816 1.01% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used 0.808366 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.677120 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1095
-system.cpu0.kern.mode_good_user 1095
+system.cpu0.kern.ipl_used_31 0.674817 # fraction of swpipl calls that actually changed the ipl
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+system.cpu0.kern.mode_good_user 1254
system.cpu0.kern.mode_good_idle 0
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system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
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system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
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-system.cpu0.kern.syscall 179 # number of syscalls executed
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-system.cpu0.kern.syscall_setgid 1 0.56% 98.32% # number of syscalls executed
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-system.cpu0.kern.syscall_setsid 2 1.12% 100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction 0.017483 # Percentage of non-idle cycles
-system.cpu0.numCycles 3734379018 # number of cpu cycles simulated
-system.cpu0.num_insts 51973218 # Number of instructions executed
-system.cpu0.num_refs 13496062 # Number of memory references
-system.cpu1.dtb.accesses 477041 # DTB accesses
-system.cpu1.dtb.acv 52 # DTB access violations
-system.cpu1.dtb.hits 4561390 # DTB hits
-system.cpu1.dtb.misses 4359 # DTB misses
-system.cpu1.dtb.read_accesses 328551 # DTB read accesses
-system.cpu1.dtb.read_acv 10 # DTB read access violations
-system.cpu1.dtb.read_hits 2657400 # DTB read hits
-system.cpu1.dtb.read_misses 3911 # DTB read misses
-system.cpu1.dtb.write_accesses 148490 # DTB write accesses
-system.cpu1.dtb.write_acv 42 # DTB write access violations
-system.cpu1.dtb.write_hits 1903990 # DTB write hits
-system.cpu1.dtb.write_misses 448 # DTB write misses
-system.cpu1.idle_fraction 0.994927 # Percentage of idle cycles
-system.cpu1.itb.accesses 1392687 # ITB accesses
-system.cpu1.itb.acv 18 # ITB acv
-system.cpu1.itb.hits 1391015 # ITB hits
-system.cpu1.itb.misses 1672 # ITB misses
-system.cpu1.kern.callpal 74370 # number of callpals executed
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+system.cpu0.not_idle_fraction 0.071850 # Percentage of non-idle cycles
+system.cpu0.numCycles 3970017178 # number of cpu cycles simulated
+system.cpu0.num_insts 52312134 # Number of instructions executed
+system.cpu0.num_refs 13564902 # Number of memory references
+system.cpu1.dtb.accesses 302962 # DTB accesses
+system.cpu1.dtb.acv 84 # DTB access violations
+system.cpu1.dtb.hits 4635665 # DTB hits
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+system.cpu1.dtb.read_accesses 205912 # DTB read accesses
+system.cpu1.dtb.read_acv 36 # DTB read access violations
+system.cpu1.dtb.read_hits 2664909 # DTB read hits
+system.cpu1.dtb.read_misses 2747 # DTB read misses
+system.cpu1.dtb.write_accesses 97050 # DTB write accesses
+system.cpu1.dtb.write_acv 48 # DTB write access violations
+system.cpu1.dtb.write_hits 1970756 # DTB write hits
+system.cpu1.dtb.write_misses 360 # DTB write misses
+system.cpu1.idle_fraction 0.974941 # Percentage of idle cycles
+system.cpu1.itb.accesses 885878 # ITB accesses
+system.cpu1.itb.acv 41 # ITB acv
+system.cpu1.itb.hits 884631 # ITB hits
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system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
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-system.cpu1.kern.callpal_wrfen 1 0.00% 0.56% # number of callpals executed
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-system.cpu1.kern.callpal_wrusp 5 0.01% 94.41% # number of callpals executed
-system.cpu1.kern.callpal_rdusp 1 0.00% 94.41% # number of callpals executed
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system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 82881 # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei 87713 # number of hwrei instructions executed
system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed
system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed
-system.cpu1.kern.inst.quiesce 2511 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count 71371 # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0 27750 38.88% 38.88% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22 1902 2.66% 41.55% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30 506 0.71% 42.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31 41213 57.74% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good 55758 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0 26928 48.29% 48.29% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22 1902 3.41% 51.71% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30 506 0.91% 52.61% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31 26422 47.39% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 3734898431 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 3704872588 99.20% 99.20% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22 224436 0.01% 99.20% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30 162482 0.00% 99.21% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31 29638925 0.79% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used 0.781242 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_0 0.970378 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 77873 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 30259 38.86% 38.86% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_good 60597 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 29300 48.35% 48.35% # number of times we switched to this ipl from a different ipl
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+system.cpu1.kern.ipl_good_30 571 0.94% 52.59% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 28729 47.41% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 3968771896 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 3847181696 96.94% 96.94% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 1867354 0.05% 96.98% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 1457952 0.04% 97.02% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 118264894 2.98% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used 0.778152 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0 0.968307 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31 0.641108 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel 1093
-system.cpu1.kern.mode_good_user 662
-system.cpu1.kern.mode_good_idle 431
-system.cpu1.kern.mode_switch_kernel 2354 # number of protection mode switches
-system.cpu1.kern.mode_switch_user 662 # number of protection mode switches
-system.cpu1.kern.mode_switch_idle 2830 # number of protection mode switches
-system.cpu1.kern.mode_switch_good 0.373931 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel 0.464316 # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31 0.637770 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 1013
+system.cpu1.kern.mode_good_user 518
+system.cpu1.kern.mode_good_idle 495
+system.cpu1.kern.mode_switch_kernel 2345 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 518 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 3028 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 0.343914 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.431983 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle 0.152297 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 13359666 0.36% 0.36% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user 1967356 0.05% 0.41% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 3719571407 99.59% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 2103 # number of times the context was actually changed
-system.cpu1.kern.syscall 150 # number of syscalls executed
-system.cpu1.kern.syscall_fork 1 0.67% 0.67% # number of syscalls executed
-system.cpu1.kern.syscall_read 16 10.67% 11.33% # number of syscalls executed
-system.cpu1.kern.syscall_close 16 10.67% 22.00% # number of syscalls executed
-system.cpu1.kern.syscall_chmod 1 0.67% 22.67% # number of syscalls executed
-system.cpu1.kern.syscall_obreak 9 6.00% 28.67% # number of syscalls executed
-system.cpu1.kern.syscall_lseek 3 2.00% 30.67% # number of syscalls executed
-system.cpu1.kern.syscall_getpid 2 1.33% 32.00% # number of syscalls executed
-system.cpu1.kern.syscall_setuid 3 2.00% 34.00% # number of syscalls executed
-system.cpu1.kern.syscall_getuid 3 2.00% 36.00% # number of syscalls executed
-system.cpu1.kern.syscall_access 5 3.33% 39.33% # number of syscalls executed
-system.cpu1.kern.syscall_open 25 16.67% 56.00% # number of syscalls executed
-system.cpu1.kern.syscall_getgid 3 2.00% 58.00% # number of syscalls executed
-system.cpu1.kern.syscall_sigprocmask 2 1.33% 59.33% # number of syscalls executed
-system.cpu1.kern.syscall_ioctl 2 1.33% 60.67% # number of syscalls executed
-system.cpu1.kern.syscall_readlink 1 0.67% 61.33% # number of syscalls executed
-system.cpu1.kern.syscall_execve 2 1.33% 62.67% # number of syscalls executed
-system.cpu1.kern.syscall_mmap 37 24.67% 87.33% # number of syscalls executed
-system.cpu1.kern.syscall_mprotect 12 8.00% 95.33% # number of syscalls executed
-system.cpu1.kern.syscall_dup2 1 0.67% 96.00% # number of syscalls executed
-system.cpu1.kern.syscall_fcntl 2 1.33% 97.33% # number of syscalls executed
-system.cpu1.kern.syscall_setgid 3 2.00% 99.33% # number of syscalls executed
-system.cpu1.kern.syscall_getrlimit 1 0.67% 100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction 0.005073 # Percentage of non-idle cycles
-system.cpu1.numCycles 3734898877 # number of cpu cycles simulated
-system.cpu1.num_insts 14364039 # Number of instructions executed
-system.cpu1.num_refs 4590544 # Number of memory references
+system.cpu1.kern.mode_switch_good_idle 0.163474 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 63013938 1.59% 1.59% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 5102326 0.13% 1.72% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 3899442912 98.28% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 2278 # number of times the context was actually changed
+system.cpu1.kern.syscall 102 # number of syscalls executed
+system.cpu1.kern.syscall_fork 2 1.96% 1.96% # number of syscalls executed
+system.cpu1.kern.syscall_read 11 10.78% 12.75% # number of syscalls executed
+system.cpu1.kern.syscall_write 1 0.98% 13.73% # number of syscalls executed
+system.cpu1.kern.syscall_close 12 11.76% 25.49% # number of syscalls executed
+system.cpu1.kern.syscall_obreak 5 4.90% 30.39% # number of syscalls executed
+system.cpu1.kern.syscall_lseek 4 3.92% 34.31% # number of syscalls executed
+system.cpu1.kern.syscall_getpid 2 1.96% 36.27% # number of syscalls executed
+system.cpu1.kern.syscall_setuid 2 1.96% 38.24% # number of syscalls executed
+system.cpu1.kern.syscall_getuid 2 1.96% 40.20% # number of syscalls executed
+system.cpu1.kern.syscall_access 3 2.94% 43.14% # number of syscalls executed
+system.cpu1.kern.syscall_open 15 14.71% 57.84% # number of syscalls executed
+system.cpu1.kern.syscall_getgid 2 1.96% 59.80% # number of syscalls executed
+system.cpu1.kern.syscall_sigprocmask 3 2.94% 62.75% # number of syscalls executed
+system.cpu1.kern.syscall_ioctl 1 0.98% 63.73% # number of syscalls executed
+system.cpu1.kern.syscall_execve 2 1.96% 65.69% # number of syscalls executed
+system.cpu1.kern.syscall_mmap 22 21.57% 87.25% # number of syscalls executed
+system.cpu1.kern.syscall_mprotect 7 6.86% 94.12% # number of syscalls executed
+system.cpu1.kern.syscall_dup2 1 0.98% 95.10% # number of syscalls executed
+system.cpu1.kern.syscall_fcntl 2 1.96% 97.06% # number of syscalls executed
+system.cpu1.kern.syscall_setgid 2 1.96% 99.02% # number of syscalls executed
+system.cpu1.kern.syscall_getrlimit 1 0.98% 100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction 0.025059 # Percentage of non-idle cycles
+system.cpu1.numCycles 3968772136 # number of cpu cycles simulated
+system.cpu1.num_insts 14633336 # Number of instructions executed
+system.cpu1.num_refs 4665250 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
Listening for console connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
warn: Entering event queue @ 0. Starting simulation...
-warn: 271343: Trying to launch CPU number 1!
+warn: 1082476: Trying to launch CPU number 1!
All Rights Reserved
-M5 compiled Oct 10 2006 01:59:16
-M5 started Tue Oct 10 02:09:13 2006
-M5 executing on zamp.eecs.umich.edu
+M5 compiled Nov 5 2006 19:41:29
+M5 started Sun Nov 5 20:04:42 2006
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-Exiting @ tick 3734898877 because m5_exit instruction encountered
+Exiting @ tick 3970017178 because m5_exit instruction encountered
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
profile=0
progress_interval=0
system=system
[system.iobus]
type=Bus
+children=responder
bus_id=0
clock=2
+responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+
[system.membus]
type=Bus
+children=responder
bus_id=1
clock=2
+responder_set=false
width=64
+default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
+pio=system.membus.default
+
[system.physmem]
type=PhysicalMemory
file=
bus_id=1
clock=2
width=64
+responder_set=false
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+itb=system.cpu.itb
+dtb=system.cpu.dtb
+profile=0
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.membus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[system.bridge]
type=Bridge
driveID=master
delay=2000
-[system.cpu.itb]
-type=AlphaITB
-size=48
-
-[system.cpu.dtb]
-type=AlphaDTB
-size=64
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-mem=system.physmem
-system=system
-cpu_id=0
-itb=system.cpu.itb
-dtb=system.cpu.dtb
-profile=0
-clock=1
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.intrctrl]
-type=IntrControl
-cpu=system.cpu
-
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
system=system
disk=system.simple_disk.disk
-[system.tsunami]
-type=Tsunami
-system=system
-intrctrl=system.intrctrl
-
[system.tsunami.fake_uart1]
type=IsaFake
pio_addr=8804615848696
bus_id=0
clock=2
width=64
+responder_set=true
+
+[system.iobus.responder]
+type=BadAddr
+pio_addr=0
+pio_latency=0
+platform=system.tsunami
+system=system
[trace]
flags=
---------- Begin Simulation Statistics ----------
-host_inst_rate 244619 # Simulator instruction rate (inst/s)
-host_mem_usage 197804 # Number of bytes of host memory used
-host_seconds 252.48 # Real time elapsed on the host
-host_tick_rate 14464234 # Simulator tick rate (ticks/s)
+host_inst_rate 351787 # Simulator instruction rate (inst/s)
+host_mem_usage 198432 # Number of bytes of host memory used
+host_seconds 175.87 # Real time elapsed on the host
+host_tick_rate 22032614 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
-sim_insts 61760478 # Number of instructions simulated
-sim_seconds 1.825937 # Number of seconds simulated
-sim_ticks 3651873858 # Number of ticks simulated
-system.cpu.dtb.accesses 1304494 # DTB accesses
+sim_insts 61868161 # Number of instructions simulated
+sim_seconds 1.937422 # Number of seconds simulated
+sim_ticks 3874844018 # Number of ticks simulated
+system.cpu.dtb.accesses 1304554 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 16545335 # DTB hits
-system.cpu.dtb.misses 11425 # DTB misses
-system.cpu.dtb.read_accesses 900425 # DTB read accesses
+system.cpu.dtb.hits 16566194 # DTB hits
+system.cpu.dtb.misses 11447 # DTB misses
+system.cpu.dtb.read_accesses 900486 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 10034117 # DTB read hits
-system.cpu.dtb.read_misses 10280 # DTB read misses
-system.cpu.dtb.write_accesses 404069 # DTB write accesses
+system.cpu.dtb.read_hits 10048141 # DTB read hits
+system.cpu.dtb.read_misses 10303 # DTB read misses
+system.cpu.dtb.write_accesses 404068 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6511218 # DTB write hits
-system.cpu.dtb.write_misses 1145 # DTB write misses
-system.cpu.idle_fraction 0.978539 # Percentage of idle cycles
-system.cpu.itb.accesses 3281311 # ITB accesses
+system.cpu.dtb.write_hits 6518053 # DTB write hits
+system.cpu.dtb.write_misses 1144 # DTB write misses
+system.cpu.idle_fraction 0.918945 # Percentage of idle cycles
+system.cpu.itb.accesses 3281349 # ITB accesses
system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 3276321 # ITB hits
-system.cpu.itb.misses 4990 # ITB misses
-system.cpu.kern.callpal 193987 # number of callpals executed
+system.cpu.itb.hits 3276346 # ITB hits
+system.cpu.itb.misses 5003 # ITB misses
+system.cpu.kern.callpal 195242 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx 4203 2.17% 2.17% # number of callpals executed
-system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
-system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl 176881 91.18% 93.38% # number of callpals executed
-system.cpu.kern.callpal_rdps 6888 3.55% 96.93% # number of callpals executed
-system.cpu.kern.callpal_wrkgp 1 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed
-system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed
-system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed
-system.cpu.kern.callpal_rti 5219 2.69% 99.63% # number of callpals executed
+system.cpu.kern.callpal_swpctx 4161 2.13% 2.13% # number of callpals executed
+system.cpu.kern.callpal_tbi 54 0.03% 2.16% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 2.16% # number of callpals executed
+system.cpu.kern.callpal_swpipl 178096 91.22% 93.38% # number of callpals executed
+system.cpu.kern.callpal_rdps 6977 3.57% 96.96% # number of callpals executed
+system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
+system.cpu.kern.callpal_rti 5212 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 213061 # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei 214344 # number of hwrei instructions executed
system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed
system.cpu.kern.inst.ivle 0 # number of ivle instructions executed
-system.cpu.kern.inst.quiesce 6207 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 184207 # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0 75390 40.93% 40.93% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21 245 0.13% 41.06% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22 1861 1.01% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 106711 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good 150152 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0 74023 49.30% 49.30% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22 1861 1.24% 50.70% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31 74023 49.30% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 3651873412 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 3611240657 98.89% 98.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21 53683 0.00% 98.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22 219598 0.01% 98.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 40359474 1.11% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used 0.815126 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_0 0.981868 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce 6112 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 185408 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 75624 40.79% 40.79% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 143 0.08% 40.87% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 1956 1.05% 41.92% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 107685 58.08% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 150613 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 74257 49.30% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 143 0.09% 49.40% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 1956 1.30% 50.70% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 74257 49.30% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 3874842234 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 3747190106 96.71% 96.71% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 122728 0.00% 96.71% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 915408 0.02% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 126613992 3.27% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used 0.812333 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_0 0.981924 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.693677 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1934
-system.cpu.kern.mode_good_user 1754
-system.cpu.kern.mode_good_idle 180
-system.cpu.kern.mode_switch_kernel 5984 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1754 # number of protection mode switches
-system.cpu.kern.mode_switch_idle 2104 # number of protection mode switches
-system.cpu.kern.mode_switch_good 0.393010 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.323195 # fraction of useful protection mode switches
+system.cpu.kern.ipl_used_31 0.689576 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1923
+system.cpu.kern.mode_good_user 1762
+system.cpu.kern.mode_good_idle 161
+system.cpu.kern.mode_switch_kernel 5967 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1762 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2072 # number of protection mode switches
+system.cpu.kern.mode_switch_good 0.392409 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.322272 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle 0.085551 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 58926919 1.61% 1.61% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 4685602 0.13% 1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 3588260889 98.26% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4204 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good_idle 0.077703 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 118227580 3.05% 3.05% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 18744852 0.48% 3.53% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 3737869794 96.47% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4162 # number of times the context was actually changed
system.cpu.kern.syscall 329 # number of syscalls executed
system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed
system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed
system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed
system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed
-system.cpu.not_idle_fraction 0.021461 # Percentage of non-idle cycles
-system.cpu.numCycles 3651873858 # number of cpu cycles simulated
-system.cpu.num_insts 61760478 # Number of instructions executed
-system.cpu.num_refs 16793874 # Number of memory references
+system.cpu.not_idle_fraction 0.081055 # Percentage of non-idle cycles
+system.cpu.numCycles 3874844018 # number of cpu cycles simulated
+system.cpu.num_insts 61868161 # Number of instructions executed
+system.cpu.num_refs 16814275 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: Entering event queue @ 0. Starting simulation...
All Rights Reserved
-M5 compiled Oct 10 2006 01:59:16
-M5 started Tue Oct 10 02:04:59 2006
-M5 executing on zamp.eecs.umich.edu
+M5 compiled Nov 5 2006 19:41:29
+M5 started Sun Nov 5 20:04:39 2006
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
-Exiting @ tick 3651873858 because m5_exit instruction encountered
+Exiting @ tick 3874844018 because m5_exit instruction encountered
max_insts_any_thread=500000
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
progress_interval=0
simulate_stalls=false
system=system
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=EioProcess
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
-mem=system.physmem
system=system
cpu_id=0
workload=system.cpu.workload
---------- Begin Simulation Statistics ----------
-host_inst_rate 1432213 # Simulator instruction rate (inst/s)
-host_mem_usage 147652 # Number of bytes of host memory used
-host_seconds 0.35 # Real time elapsed on the host
-host_tick_rate 1430432 # Simulator tick rate (ticks/s)
+host_inst_rate 1281059 # Simulator instruction rate (inst/s)
+host_mem_usage 147756 # Number of bytes of host memory used
+host_seconds 0.39 # Real time elapsed on the host
+host_tick_rate 1279755 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
All Rights Reserved
-M5 compiled Oct 8 2006 14:00:39
-M5 started Sun Oct 8 14:00:58 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:57 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Exiting @ tick 499999 because a thread reached the max instruction count
max_insts_any_thread=500000
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
progress_interval=0
system=system
workload=system.cpu.workload
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
bus_id=0
clock=1000
width=64
+responder_set=false
-[system.cpu.dcache]
+[system.cpu.workload]
+type=EioProcess
+file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.workload]
-type=EioProcess
-file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-chkpt=
-output=cout
-system=system
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=500000
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-mem=system.cpu.dcache
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
---------- Begin Simulation Statistics ----------
-host_inst_rate 66568 # Simulator instruction rate (inst/s)
-host_mem_usage 179344 # Number of bytes of host memory used
-host_seconds 7.51 # Real time elapsed on the host
-host_tick_rate 530155 # Simulator tick rate (ticks/s)
+host_inst_rate 542626 # Simulator instruction rate (inst/s)
+host_mem_usage 178896 # Number of bytes of host memory used
+host_seconds 0.92 # Real time elapsed on the host
+host_tick_rate 4319791 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000004 # Number of seconds simulated
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 180321 # number of overall hits
system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499597 # number of overall hits
system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
All Rights Reserved
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:09:55 2006
+M5 compiled Nov 3 2006 17:10:27
+M5 started Fri Nov 3 17:10:58 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Exiting @ tick 3982316 because a thread reached the max instruction count
projects / gem5.git / commitdiff