misc: Merge branch v20.1.0.3 hotfix into develop

Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d

diff --combined src/arch/arm/ArmISA.py
index bc5f823786d3dd34d37c06595255a1c66ef45e4e,0725726895422aed7d2850ac4bb24981057c365c..59d3919d51c76be8ceef4177bd4ae89787836c96
--- 1/src/arch/arm/ArmISA.py
--- 2/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@@ -1,4 -1,4 +1,4 @@@
- # Copyright (c) 2012-2013, 2015-2020 ARM Limited
+ # Copyright (c) 2012-2013, 2015-2021 ARM Limited
  # All rights reserved.
  #
  # The license below extends only to copyright in the software and shall
@@@ -36,7 -36,6 +36,7 @@@
  from m5.params import *
  from m5.proxy import *
  
 +from m5.SimObject import SimObject
  from m5.objects.ArmPMU import ArmPMU
  from m5.objects.ArmSystem import SveVectorLength
  from m5.objects.BaseISA import BaseISA
@@@ -72,7 -71,6 +72,7 @@@ class ArmISA(BaseISA)
      # SuperSec | Coherent TLB | Bcast Maint |
      # BP Maint | Cache Maint Set/way | Cache Maint MVA
      id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
 +    id_mmfr4 = Param.UInt32(0x00000000, "Memory Model Feature Register 4")
  
      # See section B4.1.84 of ARM ARM
      # All values are latest for ARMv7-A profile
@@@ -81,9 -79,7 +81,9 @@@
      id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
      id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
      id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
 -    id_isar5 = Param.UInt32(0x10000000, "Instruction Set Attribute Register 5")
 +    id_isar5 = Param.UInt32(0x11000000, "Instruction Set Attribute Register 5")
 +    # !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
 +    id_isar6 = Param.UInt32(0x00000001, "Instruction Set Attribute Register 6")
  
      fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  
@@@ -101,11 -97,10 +101,11 @@@
      id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
          "AArch64 Debug Feature Register 1")
  
 -    # !TME | !Atomic | !CRC32 | !SHA2 | !SHA1 | !AES
 -    id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
 +    # !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
 +    id_aa64isar0_el1 = Param.UInt64(0x0000000010000000,
          "AArch64 Instruction Set Attribute Register 0")
  
 +    # !I8MM | !BF16 | SPECRES = 0 | !SB |
      # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
      id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
          "AArch64 Instruction Set Attribute Register 1")
@@@ -113,11 -108,10 +113,11 @@@
      # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
      id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
          "AArch64 Memory Model Feature Register 0")
-     # PAN | HPDS | VHE
-     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101100,
+     # PAN | HPDS | !VHE
+     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
          "AArch64 Memory Model Feature Register 1")
 -    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
 +    # |VARANGE
 +    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010000,
          "AArch64 Memory Model Feature Register 2")
  
      # Any access (read/write) to an unimplemented
@@@ -130,7 -124,3 +130,7 @@@
      # allocated, instead of an ArmSystem
      sve_vl_se = Param.SveVectorLength(1,
          "SVE vector length in quadwords (128-bit), SE-mode only")
 +
 +    # Recurse into subnodes to generate DTB entries. This is mainly needed to
 +    # generate the PMU entry.
 +    generateDeviceTree = SimObject.recurseDeviceTree

diff --combined src/arch/arm/ArmSystem.py
index f7d9cd546d94d26ad26c4bb6bd1396ad4f2680d0,b2e58a3e7e163b7004c774927d8d82bac5718832..142d6c7ac096c744640c8fa873a8be4946d14a7c
--- 1/src/arch/arm/ArmSystem.py
--- 2/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@@ -1,4 -1,4 +1,4 @@@
- # Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
+ # Copyright (c) 2009, 2012-2013, 2015-2021 ARM Limited
  # All rights reserved.
  #
  # The license below extends only to copyright in the software and shall
@@@ -48,6 -48,7 +48,6 @@@ class ArmSystem(System)
      cxx_header = "arch/arm/system.hh"
      multi_proc = Param.Bool(True, "Multiprocessor system?")
      gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
 -    flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
      have_security = Param.Bool(False,
          "True if Security Extensions are implemented")
      have_virtualization = Param.Bool(False,
@@@ -59,7 -60,7 +59,7 @@@
          "Reset address (ARMv8)")
      auto_reset_addr = Param.Bool(True,
          "Determine reset address from kernel entry point if no boot loader")
 -    highest_el_is_64 = Param.Bool(False,
 +    highest_el_is_64 = Param.Bool(True,
          "True if the register width of the highest implemented exception level "
          "is 64 bits (ARMv8)")
      phys_addr_range_64 = Param.UInt8(40,
@@@ -72,6 -73,8 +72,8 @@@
          "SVE vector length in quadwords (128-bit)")
      have_lse = Param.Bool(True,
          "True if LSE is implemented (ARMv8.1)")
+     have_vhe = Param.Bool(False,
+         "True if FEAT_VHE (Virtualization Host Extensions) is implemented")
      have_pan = Param.Bool(True,
          "True if Priviledge Access Never is implemented (ARMv8.1)")
      have_secel2 = Param.Bool(True,
@@@ -108,7 -111,7 +110,7 @@@
          # root instead of appended.
  
          def generateMemNode(mem_range):
 -            node = FdtNode("memory@%x" % long(mem_range.start))
 +            node = FdtNode("memory@%x" % int(mem_range.start))
              node.append(FdtPropertyStrings("device_type", ["memory"]))
              node.append(FdtPropertyWords("reg",
                  state.addrCells(mem_range.start) +

diff --combined src/arch/arm/isa.cc
index f4fabc16a33da90aae5406e21aef4fd257b71309,8adbdabdb0af1d8e111d39ce9724225e3e5d7bc8..2429e5cb0421dbb7c1fc0483e2331ca994c0996e
--- 1/src/arch/arm/isa.cc
--- 2/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@@ -1,5 -1,5 +1,5 @@@
  /*
-  * Copyright (c) 2010-2020 ARM Limited
+  * Copyright (c) 2010-2021 ARM Limited
   * All rights reserved
   *
   * The license below extends only to copyright in the software and shall
@@@ -40,10 -40,10 +40,10 @@@
  #include "arch/arm/faults.hh"
  #include "arch/arm/htm.hh"
  #include "arch/arm/interrupts.hh"
 +#include "arch/arm/mmu.hh"
  #include "arch/arm/pmu.hh"
  #include "arch/arm/self_debug.hh"
  #include "arch/arm/system.hh"
 -#include "arch/arm/tlb.hh"
  #include "arch/arm/tlbi_op.hh"
  #include "cpu/base.hh"
  #include "cpu/checker/cpu.hh"
@@@ -60,9 -60,9 +60,9 @@@
  namespace ArmISA
  {
  
 -ISA::ISA(Params *p) : BaseISA(p), system(NULL),
 -    _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
 -    pmu(p->pmu), impdefAsNop(p->impdef_nop),
 +ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
 +    _decoderFlavor(p.decoderFlavor), _vecRegRenameMode(Enums::Full),
 +    pmu(p.pmu), impdefAsNop(p.impdef_nop),
      afterStartup(false)
  {
      miscRegs[MISCREG_SCTLR_RST] = 0;
@@@ -76,7 -76,7 +76,7 @@@
      // Give all ISA devices a pointer to this ISA
      pmu->setISA(this);
  
 -    system = dynamic_cast<ArmSystem *>(p->system);
 +    system = dynamic_cast<ArmSystem *>(p.system);
  
      // Cache system-level properties
      if (FullSystem && system) {
@@@ -88,6 -88,7 +88,7 @@@
          haveLargeAsid64 = system->haveLargeAsid64();
          physAddrRange = system->physAddrRange();
          haveSVE = system->haveSVE();
+         haveVHE = system->haveVHE();
          havePAN = system->havePAN();
          haveSecEL2 = system->haveSecEL2();
          sveVL = system->sveVL();
@@@ -100,9 -101,10 +101,10 @@@
          haveLargeAsid64 = false;
          physAddrRange = 32;  // dummy value
          haveSVE = true;
+         haveVHE = false;
          havePAN = false;
          haveSecEL2 = true;
 -        sveVL = p->sve_vl_se;
 +        sveVL = p.sve_vl_se;
          haveLSE = true;
          haveTME = true;
      }
@@@ -120,20 -122,21 +122,20 @@@
  
  std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
  
 -const ArmISAParams *
 +const ArmISAParams &
  ISA::params() const
  {
 -    return dynamic_cast<const Params *>(_params);
 +    return dynamic_cast<const Params &>(_params);
  }
  
  void
  ISA::clear()
  {
 -    const Params *p(params());
 +    const Params &p(params());
  
      // Invalidate cached copies of miscregs in the TLBs
      if (tc) {
 -        getITBPtr(tc)->invalidateMiscReg();
 -        getDTBPtr(tc)->invalidateMiscReg();
 +        getMMUPtr(tc)->invalidateMiscReg();
      }
  
      SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
@@@ -219,7 -222,7 +221,7 @@@
  }
  
  void
 -ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
 +ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
  {
      CPSR cpsr = 0;
      cpsr.mode = MODE_USER;
@@@ -248,7 -251,7 +250,7 @@@
  
      miscRegs[MISCREG_CPACR] = 0;
  
 -    miscRegs[MISCREG_FPSID] = p->fpsid;
 +    miscRegs[MISCREG_FPSID] = p.fpsid;
  
      if (haveLPAE) {
          TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
@@@ -271,7 -274,7 +273,7 @@@
  }
  
  void
 -ISA::clear64(const ArmISAParams *p)
 +ISA::clear64(const ArmISAParams &p)
  {
      CPSR cpsr = 0;
      Addr rvbar = system->resetAddr();
@@@ -320,13 -323,13 +322,13 @@@
  }
  
  void
 -ISA::initID32(const ArmISAParams *p)
 +ISA::initID32(const ArmISAParams &p)
  {
      // Initialize configurable default values
  
      uint32_t midr;
 -    if (p->midr != 0x0)
 -        midr = p->midr;
 +    if (p.midr != 0x0)
 +        midr = p.midr;
      else if (highestELIs64)
          // Cortex-A57 TRM r0p0 MIDR
          midr = 0x410fd070;
@@@ -338,19 -341,17 +340,19 @@@
      miscRegs[MISCREG_MIDR_EL1] = midr;
      miscRegs[MISCREG_VPIDR] = midr;
  
 -    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
 -    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
 -    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
 -    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
 -    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
 -    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
 +    miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
 +    miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
 +    miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
 +    miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
 +    miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
 +    miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
 +    miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
  
 -    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
 -    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
 -    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
 -    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
 +    miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
 +    miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
 +    miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
 +    miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
 +    miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
  
      miscRegs[MISCREG_ID_ISAR5] = insertBits(
          miscRegs[MISCREG_ID_ISAR5], 19, 4,
@@@ -358,24 -359,24 +360,24 @@@
  }
  
  void
 -ISA::initID64(const ArmISAParams *p)
 +ISA::initID64(const ArmISAParams &p)
  {
      // Initialize configurable id registers
 -    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
 -    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
 +    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
 +    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
      miscRegs[MISCREG_ID_AA64DFR0_EL1] =
 -        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
 -        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
 +        (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
 +        (p.pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
  
 -    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
 -    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
 -    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
 -    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
 -    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
 -    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
 +    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
 +    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
 +    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
 +    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
 +    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
 +    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
  
      miscRegs[MISCREG_ID_DFR0_EL1] =
 -        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
 +        (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
  
      miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
  
@@@ -426,6 -427,10 +428,10 @@@
      miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
          miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
          haveLSE ? 0x2 : 0x0);
+     // VHE
+     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+         miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
+         haveVHE ? 0x1 : 0x0);
      // PAN
      miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
          miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
@@@ -845,11 -850,12 +851,11 @@@ ISA::setMiscReg(int misc_reg, RegVal va
          int old_mode = old_cpsr.mode;
          CPSR cpsr = val;
          if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
 -            getITBPtr(tc)->invalidateMiscReg();
 -            getDTBPtr(tc)->invalidateMiscReg();
 +            getMMUPtr(tc)->invalidateMiscReg();
          }
  
          if (cpsr.pan != old_cpsr.pan) {
 -            getDTBPtr(tc)->invalidateMiscReg();
 +            getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
          }
  
          DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
@@@ -1364,7 -1370,8 +1370,7 @@@
              }
              break;
            case MISCREG_SCR:
 -            getITBPtr(tc)->invalidateMiscReg();
 -            getDTBPtr(tc)->invalidateMiscReg();
 +            getMMUPtr(tc)->invalidateMiscReg();
              break;
            case MISCREG_SCTLR:
              {
@@@ -1382,7 -1389,8 +1388,7 @@@
                  SCTLR new_sctlr = newVal;
                  new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
                  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
 -                getITBPtr(tc)->invalidateMiscReg();
 -                getDTBPtr(tc)->invalidateMiscReg();
 +                getMMUPtr(tc)->invalidateMiscReg();
              }
            case MISCREG_MIDR:
            case MISCREG_ID_PFR0:
@@@ -1392,7 -1400,6 +1398,7 @@@
            case MISCREG_ID_MMFR1:
            case MISCREG_ID_MMFR2:
            case MISCREG_ID_MMFR3:
 +          case MISCREG_ID_MMFR4:
            case MISCREG_ID_ISAR0:
            case MISCREG_ID_ISAR1:
            case MISCREG_ID_ISAR2:
@@@ -1704,7 -1711,7 +1710,7 @@@
              {
                  assert64();
  
 -                TLBIALL tlbiOp(EL3, true);
 +                TLBIALLEL tlbiOp(EL3, true);
                  tlbiOp(tc);
                  return;
              }
@@@ -1713,60 -1720,35 +1719,60 @@@
              {
                  assert64();
  
 -                TLBIALL tlbiOp(EL3, true);
 +                TLBIALLEL tlbiOp(EL3, true);
                  tlbiOp.broadcast(tc);
                  return;
              }
 -          // AArch64 TLB Invalidate All, EL2, Inner Shareable
 +          // AArch64 TLB Invalidate All, EL2
            case MISCREG_TLBI_ALLE2:
 -          case MISCREG_TLBI_ALLE2IS:
              {
                  assert64();
                  scr = readMiscReg(MISCREG_SCR);
  
 -                TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
 +                TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
                  tlbiOp(tc);
                  return;
              }
 +          // AArch64 TLB Invalidate All, EL2, Inner Shareable
 +          case MISCREG_TLBI_ALLE2IS:
 +            {
 +                assert64();
 +                scr = readMiscReg(MISCREG_SCR);
 +
 +                TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
 +                tlbiOp.broadcast(tc);
 +                return;
 +            }
            // AArch64 TLB Invalidate All, EL1
            case MISCREG_TLBI_ALLE1:
 +            {
 +                assert64();
 +                scr = readMiscReg(MISCREG_SCR);
 +
 +                TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
 +                tlbiOp(tc);
 +                return;
 +            }
 +          // AArch64 TLB Invalidate All, EL1, Inner Shareable
 +          case MISCREG_TLBI_ALLE1IS:
 +            {
 +                assert64();
 +                scr = readMiscReg(MISCREG_SCR);
 +
 +                TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
 +                tlbiOp.broadcast(tc);
 +                return;
 +            }
            case MISCREG_TLBI_VMALLS12E1:
 -            // @todo: handle VMID and stage 2 to enable Virtualization
              {
                  assert64();
                  scr = readMiscReg(MISCREG_SCR);
  
 -                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
 +                TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
                  tlbiOp(tc);
                  return;
              }
            case MISCREG_TLBI_VMALLE1:
 -            // @todo: handle VMID and stage 2 to enable Virtualization
              {
                  assert64();
                  scr = readMiscReg(MISCREG_SCR);
@@@ -1774,20 -1756,24 +1780,20 @@@
                  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
                  bool is_host = (hcr.tge && hcr.e2h);
                  ExceptionLevel target_el = is_host ?  EL2 : EL1;
 -                TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
 +                TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
                  tlbiOp(tc);
                  return;
              }
 -          // AArch64 TLB Invalidate All, EL1, Inner Shareable
 -          case MISCREG_TLBI_ALLE1IS:
            case MISCREG_TLBI_VMALLS12E1IS:
 -            // @todo: handle VMID and stage 2 to enable Virtualization
              {
                  assert64();
                  scr = readMiscReg(MISCREG_SCR);
  
 -                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
 +                TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
                  tlbiOp.broadcast(tc);
                  return;
              }
            case MISCREG_TLBI_VMALLE1IS:
 -            // @todo: handle VMID and stage 2 to enable Virtualization
              {
                  assert64();
                  scr = readMiscReg(MISCREG_SCR);
@@@ -1795,13 -1781,14 +1801,13 @@@
                  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
                  bool is_host = (hcr.tge && hcr.e2h);
                  ExceptionLevel target_el = is_host ?  EL2 : EL1;
 -                TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
 +                TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
                  tlbiOp.broadcast(tc);
                  return;
              }
            // VAEx(IS) and VALEx(IS) are the same because TLBs
            // only store entries
            // from the last level of translation table walks
 -          // @todo: handle VMID to enable Virtualization
            // AArch64 TLB Invalidate by VA, EL3
            case MISCREG_TLBI_VAE3_Xt:
            case MISCREG_TLBI_VALE3_Xt:
@@@ -1893,6 -1880,7 +1899,6 @@@
                  return;
              }
            // AArch64 TLB Invalidate by ASID, EL1
 -          // @todo: handle VMID to enable Virtualization
            case MISCREG_TLBI_ASIDE1_Xt:
              {
                  assert64();
@@@ -2096,7 -2084,8 +2102,7 @@@
                      newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
                  }
                  // Invalidate TLB MiscReg
 -                getITBPtr(tc)->invalidateMiscReg();
 -                getDTBPtr(tc)->invalidateMiscReg();
 +                getMMUPtr(tc)->invalidateMiscReg();
                  break;
              }
            case MISCREG_TTBR0:
@@@ -2112,7 -2101,8 +2118,7 @@@
                      }
                  }
                  // Invalidate TLB MiscReg
 -                getITBPtr(tc)->invalidateMiscReg();
 -                getDTBPtr(tc)->invalidateMiscReg();
 +                getMMUPtr(tc)->invalidateMiscReg();
                  break;
              }
            case MISCREG_SCTLR_EL1:
@@@ -2135,13 -2125,15 +2141,13 @@@
            case MISCREG_TTBR0_EL2:
            case MISCREG_TTBR1_EL2:
            case MISCREG_TTBR0_EL3:
 -            getITBPtr(tc)->invalidateMiscReg();
 -            getDTBPtr(tc)->invalidateMiscReg();
 +            getMMUPtr(tc)->invalidateMiscReg();
              break;
            case MISCREG_HCR_EL2:
              {
                  const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
                  selfDebug->setenableTDETGE((HCR)val, mdcr);
 -                getITBPtr(tc)->invalidateMiscReg();
 -                getDTBPtr(tc)->invalidateMiscReg();
 +                getMMUPtr(tc)->invalidateMiscReg();
              }
              break;
            case MISCREG_NZCV:
@@@ -2189,7 -2181,7 +2195,7 @@@
            case MISCREG_PAN:
              {
                  // PAN is affecting data accesses
 -                getDTBPtr(tc)->invalidateMiscReg();
 +                getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
  
                  CPSR cpsr = miscRegs[MISCREG_CPSR];
                  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
@@@ -2353,22 -2345,6 +2359,22 @@@ ISA::zeroSveVecRegUpperPart(VecRegConta
      }
  }
  
 +void
 +ISA::serialize(CheckpointOut &cp) const
 +{
 +    DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
 +    SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
 +}
 +
 +void
 +ISA::unserialize(CheckpointIn &cp)
 +{
 +    DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
 +    UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
 +    CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 +    updateRegMap(tmp_cpsr);
 +}
 +
  void
  ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
      BaseTLB::Mode mode, Request::Flags flags, RegVal val)
@@@ -2385,13 -2361,13 +2391,13 @@@
          val, 0, flags,  Request::funcRequestorId,
          tc->pcState().pc(), tc->contextId());
  
 -    Fault fault = getDTBPtr(tc)->translateFunctional(
 +    Fault fault = getMMUPtr(tc)->translateFunctional(
          req, tc, mode, tran_type);
  
      PAR par = 0;
      if (fault == NoFault) {
          Addr paddr = req->getPaddr();
 -        uint64_t attr = getDTBPtr(tc)->getAttr();
 +        uint64_t attr = getMMUPtr(tc)->getAttr();
          uint64_t attr1 = attr >> 56;
          if (!attr1 || attr1 ==0x44) {
              attr |= 0x100;
@@@ -2436,7 -2412,7 +2442,7 @@@ ISA::addressTranslation(TLB::ArmTransla
          val, 0, flags,  Request::funcRequestorId,
          tc->pcState().pc(), tc->contextId());
  
 -    Fault fault = getDTBPtr(tc)->translateFunctional(
 +    Fault fault = getMMUPtr(tc)->translateFunctional(
          req, tc, mode, tran_type);
  
      PAR par = 0;
@@@ -2455,7 -2431,7 +2461,7 @@@
          }
  
          par = (paddr & mask(max_paddr_bit, 12)) |
 -            (getDTBPtr(tc)->getAttr());
 +            (getMMUPtr(tc)->getAttr());
  
          DPRINTF(MiscRegs,
                 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
@@@ -2500,3 -2476,9 +2506,3 @@@ ISA::MiscRegLUTEntryInitializer::highes
  }
  
  }  // namespace ArmISA
 -
 -ArmISA::ISA *
 -ArmISAParams::create()
 -{
 -    return new ArmISA::ISA(this);
 -}

diff --combined src/arch/arm/isa.hh
index dce5e37e795757085444f5d90b757b7ca9b8e5e9,40fa561e23b5bc6d3004b0c16aa43a824683f277..133c8248a7fb01f446337ae82d516a9ba885f018
--- 1/src/arch/arm/isa.hh
--- 2/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@@ -1,5 -1,5 +1,5 @@@
  /*
-  * Copyright (c) 2010, 2012-2020 ARM Limited
+  * Copyright (c) 2010, 2012-2021 ARM Limited
   * All rights reserved
   *
   * The license below extends only to copyright in the software and shall
@@@ -94,6 -94,7 +94,7 @@@ namespace ArmIS
          uint8_t physAddrRange;
          bool haveSVE;
          bool haveLSE;
+         bool haveVHE;
          bool havePAN;
          bool haveSecEL2;
          bool haveTME;
@@@ -252,30 -253,12 +253,30 @@@
                  privNonSecureRead(v);
                  return *this;
              }
 +            chain hypE2HSecureRead(bool v = true) const {
 +                info[MISCREG_HYP_E2H_S_RD] = v;
 +                return *this;
 +            }
 +            chain hypE2HNonSecureRead(bool v = true) const {
 +                info[MISCREG_HYP_E2H_NS_RD] = v;
 +                return *this;
 +            }
              chain hypE2HRead(bool v = true) const {
 -                info[MISCREG_HYP_E2H_RD] = v;
 +                hypE2HSecureRead(v);
 +                hypE2HNonSecureRead(v);
 +                return *this;
 +            }
 +            chain hypE2HSecureWrite(bool v = true) const {
 +                info[MISCREG_HYP_E2H_S_WR] = v;
 +                return *this;
 +            }
 +            chain hypE2HNonSecureWrite(bool v = true) const {
 +                info[MISCREG_HYP_E2H_NS_WR] = v;
                  return *this;
              }
              chain hypE2HWrite(bool v = true) const {
 -                info[MISCREG_HYP_E2H_WR] = v;
 +                hypE2HSecureWrite(v);
 +                hypE2HNonSecureWrite(v);
                  return *this;
              }
              chain hypE2H(bool v = true) const {
@@@ -283,39 -266,14 +284,39 @@@
                  hypE2HWrite(v);
                  return *this;
              }
 +            chain hypSecureRead(bool v = true) const {
 +                info[MISCREG_HYP_S_RD] = v;
 +                return *this;
 +            }
 +            chain hypNonSecureRead(bool v = true) const {
 +                info[MISCREG_HYP_NS_RD] = v;
 +                return *this;
 +            }
              chain hypRead(bool v = true) const {
                  hypE2HRead(v);
 -                info[MISCREG_HYP_RD] = v;
 +                hypSecureRead(v);
 +                hypNonSecureRead(v);
 +                return *this;
 +            }
 +            chain hypSecureWrite(bool v = true) const {
 +                info[MISCREG_HYP_S_WR] = v;
 +                return *this;
 +            }
 +            chain hypNonSecureWrite(bool v = true) const {
 +                info[MISCREG_HYP_NS_WR] = v;
                  return *this;
              }
              chain hypWrite(bool v = true) const {
                  hypE2HWrite(v);
 -                info[MISCREG_HYP_WR] = v;
 +                hypSecureWrite(v);
 +                hypNonSecureWrite(v);
 +                return *this;
 +            }
 +            chain hypSecure(bool v = true) const {
 +                hypE2HSecureRead(v);
 +                hypE2HSecureWrite(v);
 +                hypSecureRead(v);
 +                hypSecureWrite(v);
                  return *this;
              }
              chain hyp(bool v = true) const {
@@@ -504,10 -462,10 +505,10 @@@
          void clear();
  
        protected:
 -        void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
 -        void clear64(const ArmISAParams *p);
 -        void initID32(const ArmISAParams *p);
 -        void initID64(const ArmISAParams *p);
 +        void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
 +        void clear64(const ArmISAParams &p);
 +        void initID32(const ArmISAParams &p);
 +        void initID64(const ArmISAParams &p);
  
          void addressTranslation(TLB::ArmTranslationType tran_type,
              BaseTLB::Mode mode, Request::Flags flags, RegVal val);
@@@ -853,8 -811,21 +854,8 @@@
          static void zeroSveVecRegUpperPart(VecRegContainer &vc,
                                             unsigned eCount);
  
 -        void
 -        serialize(CheckpointOut &cp) const override
 -        {
 -            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
 -            SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
 -        }
 -
 -        void
 -        unserialize(CheckpointIn &cp) override
 -        {
 -            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
 -            UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
 -            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 -            updateRegMap(tmp_cpsr);
 -        }
 +        void serialize(CheckpointOut &cp) const override;
 +        void unserialize(CheckpointIn &cp) override;
  
          void startup() override;
  
@@@ -883,9 -854,9 +884,9 @@@
  
          typedef ArmISAParams Params;
  
 -        const Params *params() const;
 +        const Params &params() const;
  
 -        ISA(Params *p);
 +        ISA(const Params &p);
      };
  }
  

diff --combined src/arch/arm/system.cc
index 7f5fa1313d0ef781e826586d83dd805fc4ddc872,0bbc701e92055b85934bd2bf6cf17ce29b810a04..783366dd38e791a628706f3b55ec127e27ca0358
--- 1/src/arch/arm/system.cc
--- 2/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@@ -1,5 -1,5 +1,5 @@@
  /*
-  * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
+  * Copyright (c) 2010, 2012-2013, 2015,2017-2021 ARM Limited
   * All rights reserved
   *
   * The license below extends only to copyright in the software and shall
@@@ -51,34 -51,36 +51,35 @@@
  #include "dev/arm/gic_v2.hh"
  #include "mem/physical.hh"
  
 -using namespace std;
  using namespace Linux;
  using namespace ArmISA;
  
 -ArmSystem::ArmSystem(Params *p)
 +ArmSystem::ArmSystem(const Params &p)
      : System(p),
 -      _haveSecurity(p->have_security),
 -      _haveLPAE(p->have_lpae),
 -      _haveVirtualization(p->have_virtualization),
 -      _haveCrypto(p->have_crypto),
 +      _haveSecurity(p.have_security),
 +      _haveLPAE(p.have_lpae),
 +      _haveVirtualization(p.have_virtualization),
 +      _haveCrypto(p.have_crypto),
        _genericTimer(nullptr),
        _gic(nullptr),
        _pwrCtrl(nullptr),
 -      _highestELIs64(p->highest_el_is_64),
 -      _physAddrRange64(p->phys_addr_range_64),
 -      _haveLargeAsid64(p->have_large_asid_64),
 -      _haveTME(p->have_tme),
 -      _haveSVE(p->have_sve),
 -      _sveVL(p->sve_vl),
 -      _haveLSE(p->have_lse),
 -      _haveVHE(p->have_vhe),
 -      _havePAN(p->have_pan),
 -      _haveSecEL2(p->have_secel2),
 -      semihosting(p->semihosting),
 -      multiProc(p->multi_proc)
 -{
 -      if (p->auto_reset_addr) {
 +      _highestELIs64(p.highest_el_is_64),
 +      _physAddrRange64(p.phys_addr_range_64),
 +      _haveLargeAsid64(p.have_large_asid_64),
 +      _haveTME(p.have_tme),
 +      _haveSVE(p.have_sve),
 +      _sveVL(p.sve_vl),
 +      _haveLSE(p.have_lse),
++      _haveVHE(p.have_vhe),
 +      _havePAN(p.have_pan),
 +      _haveSecEL2(p.have_secel2),
 +      semihosting(p.semihosting),
 +      multiProc(p.multi_proc)
 +{
 +    if (p.auto_reset_addr) {
          _resetAddr = workload->getEntry();
      } else {
 -        _resetAddr = p->reset_addr;
 +        _resetAddr = p.reset_addr;
          warn_if(workload->getEntry() != _resetAddr,
                  "Workload entry point %#x and reset address %#x are different",
                  workload->getEntry(), _resetAddr);
@@@ -94,7 -96,7 +95,7 @@@
  
      if (_highestELIs64 && (
              _physAddrRange64 < 32 ||
 -            _physAddrRange64 > 48 ||
 +            _physAddrRange64 > MaxPhysAddrRange ||
              (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
          fatal("Invalid physical address range (%d)\n", _physAddrRange64);
      }
@@@ -233,3 -235,9 +234,3 @@@ ArmSystem::callClearWakeRequest(ThreadC
      if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
          pwr_ctrl->clearWakeRequest(tc);
  }
 -
 -ArmSystem *
 -ArmSystemParams::create()
 -{
 -    return new ArmSystem(this);
 -}

diff --combined src/arch/arm/system.hh
index 628f15ccde91a99a43613cbe8f4cb303b676240e,eb4da9444620d2a4d93162da06a496eff06538c8..1db60247f3c0820e75906859b88607f41da5e656
--- 1/src/arch/arm/system.hh
--- 2/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@@ -1,5 -1,5 +1,5 @@@
  /*
-  * Copyright (c) 2010, 2012-2013, 2015-2020 ARM Limited
+  * Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
   * All rights reserved
   *
   * The license below extends only to copyright in the software and shall
@@@ -130,6 -130,9 +130,9 @@@ class ArmSystem : public Syste
       */
      const bool _haveLSE;
  
+     /** True if FEAT_VHE (Virtualization Host Extensions) is implemented */
+     const bool _haveVHE;
+ 
      /** True if Priviledge Access Never is implemented */
      const unsigned _havePAN;
  
@@@ -146,13 -149,13 +149,13 @@@
      static constexpr Addr PageShift = ArmISA::PageShift;
  
      typedef ArmSystemParams Params;
 -    const Params *
 +    const Params &
      params() const
      {
 -        return dynamic_cast<const Params *>(_params);
 +        return dynamic_cast<const Params &>(_params);
      }
  
 -    ArmSystem(Params *p);
 +    ArmSystem(const Params &p);
  
      /** true if this a multiprocessor system */
      bool multiProc;
@@@ -236,6 -239,9 +239,9 @@@
      /** Returns true if LSE is implemented (ARMv8.1) */
      bool haveLSE() const { return _haveLSE; }
  
+     /** Returns true if Virtualization Host Extensions is implemented */
+     bool haveVHE() const { return _haveVHE; }
+ 
      /** Returns true if Priviledge Access Never is implemented */
      bool havePAN() const { return _havePAN; }