i965: Remove the gen6 emit_mi_flushes I sprinkled around the driver.
authorEric Anholt <eric@anholt.net>
Tue, 19 Oct 2010 16:50:44 +0000 (09:50 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 19 Oct 2010 17:49:19 +0000 (10:49 -0700)
These were for debugging in bringup.  Now that relatively complicated
apps are working, they haven't helped debug anything in quite a while.

src/mesa/drivers/dri/i965/brw_misc_state.c
src/mesa/drivers/dri/i965/gen6_cc.c
src/mesa/drivers/dri/i965/gen6_clip_state.c
src/mesa/drivers/dri/i965/gen6_gs_state.c
src/mesa/drivers/dri/i965/gen6_sampler_state.c
src/mesa/drivers/dri/i965/gen6_sf_state.c
src/mesa/drivers/dri/i965/gen6_urb.c
src/mesa/drivers/dri/i965/gen6_viewport_state.c
src/mesa/drivers/dri/i965/gen6_vs_state.c
src/mesa/drivers/dri/i965/gen6_wm_state.c

index 27d161db413f0e2b087ff0fc9caa9e31d1e0af85..24041e57b00161755c360a284bbf3e5cc6b85ee1 100644 (file)
@@ -515,8 +515,6 @@ static void upload_invarient_state( struct brw_context *brw )
    if (intel->gen >= 6) {
       int i;
 
-      intel_batchbuffer_emit_mi_flush(intel->batch);
-
       BEGIN_BATCH(3);
       OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
index 4a98e2686241967af61c4c7a061b7264e9b0a0f8..0d6e923f734490b80375a7c23ec7d55bd9e66bee 100644 (file)
@@ -271,8 +271,6 @@ static void upload_cc_state_pointers(struct brw_context *brw)
    OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 
index bf53146f11fa400cd04a99be96354ec7ae0dc7b2..cd2ac9d92fe66eda1aecad6958643d185db5d5aa 100644 (file)
@@ -61,8 +61,6 @@ upload_clip_state(struct brw_context *brw)
             provoking);
    OUT_BATCH(GEN6_CLIP_FORCE_ZERO_RTAINDEX);
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_clip_state = {
index cefc93ba48b13fed9482231f98cd5c8b3ed9b86c..6127b9197a1b880acaaecc6d83ed4e509b849e51 100644 (file)
@@ -44,8 +44,6 @@ upload_gs_state(struct brw_context *brw)
    OUT_BATCH(0);
    ADVANCE_BATCH();
 
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    if (brw->gs.prog_bo) {
       BEGIN_BATCH(7);
       OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
index ab8e7516d23b23095dd5efd00bb90af2c3d061f8..fc5d391c3cfe132593fad2307d3249c14d66c8fe 100644 (file)
@@ -49,8 +49,6 @@ upload_sampler_state_pointers(struct brw_context *brw)
       OUT_BATCH(0);
 
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 
index 377b3a41bdd437968d6ff84e840fbcac5fa02851..55a70bea62f57a89ce73dfd317eb2bbb8f3aed0a 100644 (file)
@@ -187,8 +187,6 @@ upload_sf_state(struct brw_context *brw)
    OUT_BATCH(0); /* wrapshortest enables 0-7 */
    OUT_BATCH(0); /* wrapshortest enables 8-15 */
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_sf_state = {
index 5445e4035a98d5a76e75743339d923741ff87e2e..0a264fcd90ea227495dce80d0491643fd824bfb2 100644 (file)
@@ -59,8 +59,6 @@ upload_urb(struct brw_context *brw)
    /* GS requirement */
    assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
 
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    BEGIN_BATCH(3);
    OUT_BATCH(CMD_URB << 16 | (3 - 2));
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
@@ -68,8 +66,6 @@ upload_urb(struct brw_context *brw)
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
             ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_urb = {
index b515e7712edb537943a559501b2cbb581a088eb6..d691bbebc83f9cde921090ee04e3235cd00520e2 100644 (file)
@@ -125,8 +125,6 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
    OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_viewport_state = {
index 3eca4e971b1199dd3f997c38b03231d53fcaf6dd..304eaddf409c6a8025b68f1a2936157000219fe9 100644 (file)
@@ -88,8 +88,6 @@ upload_vs_state(struct brw_context *brw)
       drm_intel_bo_unreference(constant_bo);
    }
 
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    BEGIN_BATCH(6);
    OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
    OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
@@ -103,8 +101,6 @@ upload_vs_state(struct brw_context *brw)
             GEN6_VS_STATISTICS_ENABLE |
             GEN6_VS_ENABLE);
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_vs_state = {
index 58102666354bdd96da489e374b6ae8bb3c074f13..7ef99eea6277c696772c2e4710660460c5d957b1 100644 (file)
@@ -109,8 +109,6 @@ upload_wm_state(struct brw_context *brw)
       ADVANCE_BATCH();
    }
 
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    dw2 = dw4 = dw5 = dw6 = 0;
    dw4 |= GEN6_WM_STATISTICS_ENABLE;
    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
@@ -167,8 +165,6 @@ upload_wm_state(struct brw_context *brw)
    OUT_BATCH(0); /* kernel 1 pointer */
    OUT_BATCH(0); /* kernel 2 pointer */
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_wm_state = {