if (intel->gen >= 6) {
int i;
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
BEGIN_BATCH(3);
OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
provoking);
OUT_BATCH(GEN6_CLIP_FORCE_ZERO_RTAINDEX);
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_clip_state = {
OUT_BATCH(0);
ADVANCE_BATCH();
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
if (brw->gs.prog_bo) {
BEGIN_BATCH(7);
OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
OUT_BATCH(0); /* wrapshortest enables 0-7 */
OUT_BATCH(0); /* wrapshortest enables 8-15 */
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_sf_state = {
/* GS requirement */
assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
BEGIN_BATCH(3);
OUT_BATCH(CMD_URB << 16 | (3 - 2));
OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_urb = {
OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_viewport_state = {
drm_intel_bo_unreference(constant_bo);
}
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
BEGIN_BATCH(6);
OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
GEN6_VS_STATISTICS_ENABLE |
GEN6_VS_ENABLE);
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_vs_state = {
ADVANCE_BATCH();
}
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
dw2 = dw4 = dw5 = dw6 = 0;
dw4 |= GEN6_WM_STATISTICS_ENABLE;
dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
OUT_BATCH(0); /* kernel 1 pointer */
OUT_BATCH(0); /* kernel 2 pointer */
ADVANCE_BATCH();
-
- intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_wm_state = {