Add missing RISC-V fsrmi and fsflagsi instructions.

	PR 22599
	gas/
	* testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index dcc4cb8ea976a4dee36409e147e6dee57218752b..8b24b65e4371610485d30ce66b4e42b88913d9d2 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-12-13  Jim Wilson  <jimw@sifive.com>
+
+       PR 22599
+       * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
+
 2017-12-13  Dimitar Dimitrov  <dimitar@dinux.eu>
 
        * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM

diff --git a/gas/testsuite/gas/riscv/fsxxi.d b/gas/testsuite/gas/riscv/fsxxi.d
new file mode 100644 (file)
index 0000000..2e03a20
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fsxxi.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[      ]+0:[   ]+002fd573[     ]+fsrmi[        ]+a0,31
+[      ]+4:[   ]+002f5073[     ]+fsrmi[        ]+zero,30
+[      ]+8:[   ]+001ed773[     ]+fsflagsi[     ]+a4,29
+[      ]+c:[   ]+001e5073[     ]+fsflagsi[     ]+zero,28

diff --git a/gas/testsuite/gas/riscv/fsxxi.s b/gas/testsuite/gas/riscv/fsxxi.s
new file mode 100644 (file)
index 0000000..e42d786
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fsxxi.s
@@ -0,0 +1,4 @@
+       fsrmi x10, 0x1f
+       fsrmi 0x1e
+       fsflagsi x14, 0x1d
+       fsflagsi 0x1c

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5e8ad9f7237a294df2252aa5e2ec9f2c95f83b23..dbc29fafb4a790a1350fa2495168814d09afd4f0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-12-13  Jim Wilson  <jimw@sifive.com>
+
+       PR 22599
+       * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
+
 2017-12-13  Dimitar Dimitrov  <dimitar@dinux.eu>
 
        * disassemble.c: Enable disassembler_needs_relocs for PRU.

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 84cdea8fca8fbd336994e1b978ad273772ca8a97..10448dac964b88da32c7222ea2f189ecc61a8512 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -440,9 +440,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"frrm",      "F",   "d",  MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
 {"fsrm",      "F",   "s",  MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
 {"fsrm",      "F",   "d,s",  MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
+{"fsrmi",     "F",   "d,Z",  MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 },
+{"fsrmi",     "F",   "Z",  MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 },
 {"frflags",   "F",   "d",  MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
 {"fsflags",   "F",   "s",  MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
 {"fsflags",   "F",   "d,s",  MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
+{"fsflagsi",  "F",   "d,Z",  MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 },
+{"fsflagsi",  "F",   "Z",  MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 },
 {"flw",       "32C", "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS },
 {"flw",       "32C", "CD,Ck(Cs)",  MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS },
 {"flw",       "F",   "D,o(s)",  MATCH_FLW, MASK_FLW, match_opcode, 0 },