struct brw_reg dst,
struct brw_reg index)
{
+ if (intel->gen == 7) {
+ gen6_resolve_implied_move(p, &index, inst->base_mrf);
+ brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
+ brw_set_dest(p, insn, dst);
+ brw_set_src0(p, insn, index);
+ brw_set_sampler_message(p, insn,
+ SURF_INDEX_VERT_CONST_BUFFER,
+ 0, /* LD message ignores sampler unit */
+ GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+ 1, /* rlen */
+ 1, /* mlen */
+ false, /* no header */
+ BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+ 0);
+ return;
+ }
+
struct brw_reg header = brw_vec8_grf(0, 0);
gen6_resolve_implied_move(p, &header, inst->base_mrf);