detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
+ #if 0
int width = std::max(left.width, right.width);
if (width > width_hint && width_hint > 0)
width = width_hint;
if (type == AST_MUL)
width = std::min(left.width + right.width, width_hint);
}
+ #else
+ int width = std::max(std::max(left.width, right.width), width_hint);
+ #endif
is_signed = children[0]->is_signed && children[1]->is_signed;
return binop2rtlil(this, type_name, width, left, right);
}
static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos)
{
+ if (undef_bit_pos >= 0)
+ return RTLIL::Const(RTLIL::State::Sx, result_len);
+
BigUnsigned mag = val.getMagnitude();
RTLIL::Const result(0, result_len);
}
}
+#if 0
if (undef_bit_pos >= 0)
for (int i = undef_bit_pos; i < result_len; i++)
result.bits[i] = RTLIL::State::Sx;
+#endif
return result;
}