[opcodes, pk, sim, xcc] Tweaked FP encoding

diff --git a/riscv/decode.h b/riscv/decode.h
index 327da6ccf4dde7a0918ab308f313fe48b68e503a..903eef53b659c3647bbe0b099130bdc73adc53c0 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -185,7 +185,8 @@ private:
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
-#define RM (insn.ftype.ffunct & 3)
+#define RM ((insn.ftype.ffunct & 4) ? (insn.ftype.ffunct & 3) : \
+            ((fsr & FSR_RD) >> FSR_RD_SHIFT))
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction

diff --git a/riscv/execute.h b/riscv/execute.h
index be90e6fbe1e574173986272b9a78ec9ff3e82334..02523fec40e8e97d753db49433fc1611a5cbe390 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -156,16 +156,26 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninj_s.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd4070000)
+        if((insn.bits & 0xff8ffc00) == 0xd4050000)
+        {
+          #include "insns/cvt_w_s.h"
+          break;
+        }
+        if((insn.bits & 0xff8ffc00) == 0xd4070000)
         {
           #include "insns/cvt_s_w.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd4000000)
+        if((insn.bits & 0xff8f8000) == 0xd4000000)
         {
           #include "insns/add_s.h"
           break;
         }
+        if((insn.bits & 0xff8ffc00) == 0xd4048000)
+        {
+          #include "insns/cvtu_l_s.h"
+          break;
+        }
         if((insn.bits & 0xffff83e0) == 0xd42c0000)
         {
           #include "insns/mff_s.h"
@@ -181,27 +191,27 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninjn_s.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd4078000)
+        if((insn.bits & 0xff8ffc00) == 0xd4040000)
         {
-          #include "insns/cvtu_s_w.h"
+          #include "insns/cvt_l_s.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd4068000)
+        if((insn.bits & 0xff8ffc00) == 0xd4078000)
         {
-          #include "insns/cvtu_s_l.h"
+          #include "insns/cvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd4060000)
+        if((insn.bits & 0xff8ffc00) == 0xd4068000)
         {
-          #include "insns/cvt_s_l.h"
+          #include "insns/cvtu_s_l.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd4008000)
+        if((insn.bits & 0xff8f8000) == 0xd4008000)
         {
           #include "insns/sub_s.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd4020000)
+        if((insn.bits & 0xff8ffc00) == 0xd4020000)
         {
           #include "insns/sqrt_s.h"
           break;
@@ -216,12 +226,17 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgnmul_s.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd4018000)
+        if((insn.bits & 0xff8ffc00) == 0xd4060000)
+        {
+          #include "insns/cvt_s_l.h"
+          break;
+        }
+        if((insn.bits & 0xff8f8000) == 0xd4018000)
         {
           #include "insns/div_s.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd4098000)
+        if((insn.bits & 0xff8ffc00) == 0xd4098000)
         {
           #include "insns/cvt_s_d.h"
           break;
@@ -231,89 +246,25 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/c_le_s.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd4010000)
+        if((insn.bits & 0xff8f8000) == 0xd4010000)
         {
           #include "insns/mul_s.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        if((insn.bits & 0xffcffc00) == 0xd4478000)
+        if((insn.bits & 0xff8ffc00) == 0xd4058000)
         {
-          #include "insns/cvtu_s_w_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4440000)
-        {
-          #include "insns/cvt_l_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4468000)
-        {
-          #include "insns/cvtu_s_l_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd4410000)
-        {
-          #include "insns/mul_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4448000)
-        {
-          #include "insns/cvtu_l_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4470000)
-        {
-          #include "insns/cvt_s_w_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4420000)
-        {
-          #include "insns/sqrt_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4498000)
-        {
-          #include "insns/cvt_s_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd4408000)
-        {
-          #include "insns/sub_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd4418000)
-        {
-          #include "insns/div_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4460000)
-        {
-          #include "insns/cvt_s_l_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd4400000)
-        {
-          #include "insns/add_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4450000)
-        {
-          #include "insns/cvt_w_s_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd4458000)
-        {
-          #include "insns/cvtu_w_s_rm.h"
+          #include "insns/cvtu_w_s.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x6:
       {
+        if((insn.bits & 0xff8ffc00) == 0xd5850000)
+        {
+          #include "insns/cvt_w_d.h"
+          break;
+        }
         if((insn.bits & 0xffff83e0) == 0xd5ac0000)
         {
           #include "insns/mff_d.h"
@@ -324,7 +275,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninj_d.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd5818000)
+        if((insn.bits & 0xff8f8000) == 0xd5818000)
         {
           #include "insns/div_d.h"
           break;
@@ -334,7 +285,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/c_eq_d.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd5868000)
+        if((insn.bits & 0xff8ffc00) == 0xd5868000)
         {
           #include "insns/cvtu_d_l.h"
           break;
@@ -344,6 +295,11 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/cvtu_d_w.h"
           break;
         }
+        if((insn.bits & 0xff8ffc00) == 0xd5848000)
+        {
+          #include "insns/cvtu_l_d.h"
+          break;
+        }
         if((insn.bits & 0xffff83e0) == 0xd5ac8000)
         {
           #include "insns/mffl_d.h"
@@ -354,7 +310,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgnmul_d.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd5800000)
+        if((insn.bits & 0xff8f8000) == 0xd5800000)
         {
           #include "insns/add_d.h"
           break;
@@ -379,7 +335,12 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/mtflh_d.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd5808000)
+        if((insn.bits & 0xff8ffc00) == 0xd5840000)
+        {
+          #include "insns/cvt_l_d.h"
+          break;
+        }
+        if((insn.bits & 0xff8f8000) == 0xd5808000)
         {
           #include "insns/sub_d.h"
           break;
@@ -389,7 +350,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/mtf_d.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd5820000)
+        if((insn.bits & 0xff8ffc00) == 0xd5820000)
         {
           #include "insns/sqrt_d.h"
           break;
@@ -404,78 +365,24 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/cvt_d_w.h"
           break;
         }
-        if((insn.bits & 0xfffffc00) == 0xd5860000)
+        if((insn.bits & 0xff8ffc00) == 0xd5860000)
         {
           #include "insns/cvt_d_l.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd5810000)
+        if((insn.bits & 0xff8f8000) == 0xd5810000)
         {
           #include "insns/mul_d.h"
           break;
         }
-        if((insn.bits & 0xffff8000) == 0xd58b0000)
-        {
-          #include "insns/c_lt_d.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        if((insn.bits & 0xffcffc00) == 0xd5c60000)
-        {
-          #include "insns/cvt_d_l_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd5c50000)
+        if((insn.bits & 0xff8ffc00) == 0xd5858000)
         {
-          #include "insns/cvt_w_d_rm.h"
+          #include "insns/cvtu_w_d.h"
           break;
         }
-        if((insn.bits & 0xffcffc00) == 0xd5c58000)
-        {
-          #include "insns/cvtu_w_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd5c20000)
-        {
-          #include "insns/sqrt_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd5c68000)
-        {
-          #include "insns/cvtu_d_l_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd5c00000)
-        {
-          #include "insns/add_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd5c40000)
-        {
-          #include "insns/cvt_l_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcffc00) == 0xd5c48000)
-        {
-          #include "insns/cvtu_l_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd5c10000)
-        {
-          #include "insns/mul_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd5c18000)
-        {
-          #include "insns/div_d_rm.h"
-          break;
-        }
-        if((insn.bits & 0xffcf8000) == 0xd5c08000)
+        if((insn.bits & 0xffff8000) == 0xd58b0000)
         {
-          #include "insns/sub_d_rm.h"
+          #include "insns/c_lt_d.h"
           break;
         }
         #include "insns/unimp.h"
@@ -541,30 +448,12 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfff00000) == 0xd8000000)
-        {
-          #include "insns/madd_s.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        #include "insns/madd_s_rm.h"
+        #include "insns/madd_s.h"
         break;
       }
       case 0x6:
       {
-        if((insn.bits & 0xfff00000) == 0xd9800000)
-        {
-          #include "insns/madd_d.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        #include "insns/madd_d_rm.h"
+        #include "insns/madd_d.h"
         break;
       }
       default:
@@ -580,30 +469,12 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfff00000) == 0xda000000)
-        {
-          #include "insns/msub_s.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        #include "insns/msub_s_rm.h"
+        #include "insns/msub_s.h"
         break;
       }
       case 0x6:
       {
-        if((insn.bits & 0xfff00000) == 0xdb800000)
-        {
-          #include "insns/msub_d.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        #include "insns/msub_d_rm.h"
+        #include "insns/msub_d.h"
         break;
       }
       default:
@@ -619,30 +490,12 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfff00000) == 0xdc000000)
-        {
-          #include "insns/nmsub_s.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        #include "insns/nmsub_s_rm.h"
+        #include "insns/nmsub_s.h"
         break;
       }
       case 0x6:
       {
-        if((insn.bits & 0xfff00000) == 0xdd800000)
-        {
-          #include "insns/nmsub_d.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        #include "insns/nmsub_d_rm.h"
+        #include "insns/nmsub_d.h"
         break;
       }
       default:
@@ -658,30 +511,12 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfff00000) == 0xde000000)
-        {
-          #include "insns/nmadd_s.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        #include "insns/nmadd_s_rm.h"
+        #include "insns/nmadd_s.h"
         break;
       }
       case 0x6:
       {
-        if((insn.bits & 0xfff00000) == 0xdf800000)
-        {
-          #include "insns/nmadd_d.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        #include "insns/nmadd_d_rm.h"
+        #include "insns/nmadd_d.h"
         break;
       }
       default:

diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h
index f467eb6aa501999b89e9fb6bf10804e3183e126d..48c76a77ac5b3e5bec563ff63ae7d81eae2e44a0 100644 (file)
--- a/riscv/insns/add_d.h
+++ b/riscv/insns/add_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/add_d_rm.h b/riscv/insns/add_d_rm.h
deleted file mode 100644 (file)
index 48c76a7..0000000
--- a/riscv/insns/add_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_add(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h
index edae853790cae60a5e99f0b9e98b4b596547056a..2fd5429c481d54f95087ba41460354ad66015c27 100644 (file)
--- a/riscv/insns/add_s.h
+++ b/riscv/insns/add_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/add_s_rm.h b/riscv/insns/add_s_rm.h
deleted file mode 100644 (file)
index 2fd5429..0000000
--- a/riscv/insns/add_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_add(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 28a03a915a3d1be95f3eda7e027ceaf06e111507..84c1a712be2de1b17dd29b279f9e0c8141d4896f 100644 (file)
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,4 +1,5 @@
 require64;
 require_fp;
+softfloat_roundingMode = RM;
 FRD = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_l_rm.h b/riscv/insns/cvt_d_l_rm.h
deleted file mode 100644 (file)
index 84c1a71..0000000
--- a/riscv/insns/cvt_d_l_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h
index 8e2b2f8529359b6b70cd8110127954570c0796dd..6b1a09cc5e604cbd31ff3bbc97631ca74fc334f1 100644 (file)
--- a/riscv/insns/cvt_d_s.h
+++ b/riscv/insns/cvt_d_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_s_rm.h b/riscv/insns/cvt_d_s_rm.h
deleted file mode 100644 (file)
index 6b1a09c..0000000
--- a/riscv/insns/cvt_d_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_to_f64(FRS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
index 94cd7703687bbba15746087a68369ba793033c71..638a5eca630b1f6d4b7b4dbb49ad08eb38a1cb81 100644 (file)
--- a/riscv/insns/cvt_d_w.h
+++ b/riscv/insns/cvt_d_w.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = i32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w_rm.h b/riscv/insns/cvt_d_w_rm.h
deleted file mode 100644 (file)
index 638a5ec..0000000
--- a/riscv/insns/cvt_d_w_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i32_to_f64(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_l_d.h b/riscv/insns/cvt_l_d.h
new file mode 100644 (file)
index 0000000..2747d67
--- /dev/null
+++ b/riscv/insns/cvt_l_d.h
@@ -0,0 +1,5 @@
+require64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvt_l_d_rm.h b/riscv/insns/cvt_l_d_rm.h
deleted file mode 100644 (file)
index 2747d67..0000000
--- a/riscv/insns/cvt_l_d_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_l_s.h b/riscv/insns/cvt_l_s.h
new file mode 100644 (file)
index 0000000..f5b053c
--- /dev/null
+++ b/riscv/insns/cvt_l_s.h
@@ -0,0 +1,5 @@
+require64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvt_l_s_rm.h b/riscv/insns/cvt_l_s_rm.h
deleted file mode 100644 (file)
index f5b053c..0000000
--- a/riscv/insns/cvt_l_s_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h
index 1c9b281df2fb0eab4bafa9f402bb1782cbf82f85..e5289c4b0d1866f19744089b0d93b6ef9aef3c7a 100644 (file)
--- a/riscv/insns/cvt_s_d.h
+++ b/riscv/insns/cvt_s_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_d_rm.h b/riscv/insns/cvt_s_d_rm.h
deleted file mode 100644 (file)
index e5289c4..0000000
--- a/riscv/insns/cvt_s_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_to_f32(FRS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index c89657d2381c10ffc7d74034d1772a588ab7c037..79fbc97af4e130ba08d700a9e0b8080b67c8e0d4 100644 (file)
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,4 +1,5 @@
 require64;
 require_fp;
+softfloat_roundingMode = RM;
 FRD = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l_rm.h b/riscv/insns/cvt_s_l_rm.h
deleted file mode 100644 (file)
index 79fbc97..0000000
--- a/riscv/insns/cvt_s_l_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index b11d7836d328d4f021c3c7964a01df5a16fb20cf..12b1e733f3031bb5e89ea4f3df235f520a3b147c 100644 (file)
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = i32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w_rm.h b/riscv/insns/cvt_s_w_rm.h
deleted file mode 100644 (file)
index 12b1e73..0000000
--- a/riscv/insns/cvt_s_w_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i32_to_f32(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_w_d.h b/riscv/insns/cvt_w_d.h
new file mode 100644 (file)
index 0000000..e924467
--- /dev/null
+++ b/riscv/insns/cvt_w_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i32_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvt_w_d_rm.h b/riscv/insns/cvt_w_d_rm.h
deleted file mode 100644 (file)
index e924467..0000000
--- a/riscv/insns/cvt_w_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i32_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvt_w_s.h b/riscv/insns/cvt_w_s.h
new file mode 100644 (file)
index 0000000..809797f
--- /dev/null
+++ b/riscv/insns/cvt_w_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i32_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvt_w_s_rm.h b/riscv/insns/cvt_w_s_rm.h
deleted file mode 100644 (file)
index 809797f..0000000
--- a/riscv/insns/cvt_w_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i32_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 28a03a915a3d1be95f3eda7e027ceaf06e111507..84c1a712be2de1b17dd29b279f9e0c8141d4896f 100644 (file)
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,4 +1,5 @@
 require64;
 require_fp;
+softfloat_roundingMode = RM;
 FRD = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l_rm.h b/riscv/insns/cvtu_d_l_rm.h
deleted file mode 100644 (file)
index 84c1a71..0000000
--- a/riscv/insns/cvtu_d_l_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
index 6a74d2d28c3d791cb4bb11ead2898ff5f2622465..2757790f1500d43986cfcf0970ec006f80d256d7 100644 (file)
--- a/riscv/insns/cvtu_d_w.h
+++ b/riscv/insns/cvtu_d_w.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = ui32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w_rm.h b/riscv/insns/cvtu_d_w_rm.h
deleted file mode 100644 (file)
index 2757790..0000000
--- a/riscv/insns/cvtu_d_w_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = ui32_to_f64(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_l_d.h b/riscv/insns/cvtu_l_d.h
new file mode 100644 (file)
index 0000000..2747d67
--- /dev/null
+++ b/riscv/insns/cvtu_l_d.h
@@ -0,0 +1,5 @@
+require64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvtu_l_d_rm.h b/riscv/insns/cvtu_l_d_rm.h
deleted file mode 100644 (file)
index 2747d67..0000000
--- a/riscv/insns/cvtu_l_d_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_l_s.h b/riscv/insns/cvtu_l_s.h
new file mode 100644 (file)
index 0000000..f5b053c
--- /dev/null
+++ b/riscv/insns/cvtu_l_s.h
@@ -0,0 +1,5 @@
+require64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvtu_l_s_rm.h b/riscv/insns/cvtu_l_s_rm.h
deleted file mode 100644 (file)
index f5b053c..0000000
--- a/riscv/insns/cvtu_l_s_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index c89657d2381c10ffc7d74034d1772a588ab7c037..79fbc97af4e130ba08d700a9e0b8080b67c8e0d4 100644 (file)
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,4 +1,5 @@
 require64;
 require_fp;
+softfloat_roundingMode = RM;
 FRD = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l_rm.h b/riscv/insns/cvtu_s_l_rm.h
deleted file mode 100644 (file)
index 79fbc97..0000000
--- a/riscv/insns/cvtu_s_l_rm.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index 79bb8295e9be7bb71154f17e6f670e391978dae1..4c53c01ed02d5786fa61f5e67fef466676ce0bdf 100644 (file)
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = ui32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w_rm.h b/riscv/insns/cvtu_s_w_rm.h
deleted file mode 100644 (file)
index 4c53c01..0000000
--- a/riscv/insns/cvtu_s_w_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = ui32_to_f32(RS1);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_w_d.h b/riscv/insns/cvtu_w_d.h
new file mode 100644 (file)
index 0000000..93860e8
--- /dev/null
+++ b/riscv/insns/cvtu_w_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_ui32_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvtu_w_d_rm.h b/riscv/insns/cvtu_w_d_rm.h
deleted file mode 100644 (file)
index 93860e8..0000000
--- a/riscv/insns/cvtu_w_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_ui32_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/cvtu_w_s.h b/riscv/insns/cvtu_w_s.h
new file mode 100644 (file)
index 0000000..04b8fb2
--- /dev/null
+++ b/riscv/insns/cvtu_w_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_ui32_r_minMag(FRS1,true);
+set_fp_exceptions;

diff --git a/riscv/insns/cvtu_w_s_rm.h b/riscv/insns/cvtu_w_s_rm.h
deleted file mode 100644 (file)
index 04b8fb2..0000000
--- a/riscv/insns/cvtu_w_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_ui32_r_minMag(FRS1,true);
-set_fp_exceptions;

diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
index 9f756f0fd8ba0aaeb6ef1364c51f913ecd1e17fe..aa00c98dcae8ae2e77c30f0e3ed933fa52619c1e 100644 (file)
--- a/riscv/insns/div_d.h
+++ b/riscv/insns/div_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/div_d_rm.h b/riscv/insns/div_d_rm.h
deleted file mode 100644 (file)
index aa00c98..0000000
--- a/riscv/insns/div_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_div(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
index e70d085eafde70e0522735e49543e52885fdd59c..8c765875180928f81f702fd28c119ed94b168e57 100644 (file)
--- a/riscv/insns/div_s.h
+++ b/riscv/insns/div_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/div_s_rm.h b/riscv/insns/div_s_rm.h
deleted file mode 100644 (file)
index 8c76587..0000000
--- a/riscv/insns/div_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_div(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/madd_d.h b/riscv/insns/madd_d.h
index 41de61385ccb8fdce77b80bc27aa1c8ef024bc18..f67853eef3ebdab480a54d453c19f0a8e4df422e 100644 (file)
--- a/riscv/insns/madd_d.h
+++ b/riscv/insns/madd_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/madd_d_rm.h b/riscv/insns/madd_d_rm.h
deleted file mode 100644 (file)
index f67853e..0000000
--- a/riscv/insns/madd_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3);
-set_fp_exceptions;

diff --git a/riscv/insns/madd_s.h b/riscv/insns/madd_s.h
index ee26e3cdebecde4b082bc6a13ac91006a6d2b6bb..19db6421fd2f66d121f69d0df12b17514cdfabf2 100644 (file)
--- a/riscv/insns/madd_s.h
+++ b/riscv/insns/madd_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/madd_s_rm.h b/riscv/insns/madd_s_rm.h
deleted file mode 100644 (file)
index 19db642..0000000
--- a/riscv/insns/madd_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3);
-set_fp_exceptions;

diff --git a/riscv/insns/msub_d.h b/riscv/insns/msub_d.h
index f3da45186d9ae055723ff2a169790f66c4e3aeff..b1e93408f85abc46b8b99fb21405577dcf43152c 100644 (file)
--- a/riscv/insns/msub_d.h
+++ b/riscv/insns/msub_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/msub_d_rm.h b/riscv/insns/msub_d_rm.h
deleted file mode 100644 (file)
index b1e9340..0000000
--- a/riscv/insns/msub_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
-set_fp_exceptions;

diff --git a/riscv/insns/msub_s.h b/riscv/insns/msub_s.h
index 170e1a161288f8290e3dfbd703ceb493ace78a9a..d3349f5a32eb82ceeb453c269996f08027bed82e 100644 (file)
--- a/riscv/insns/msub_s.h
+++ b/riscv/insns/msub_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/msub_s_rm.h b/riscv/insns/msub_s_rm.h
deleted file mode 100644 (file)
index d3349f5..0000000
--- a/riscv/insns/msub_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
-set_fp_exceptions;

diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h
index 6038728b66e1d6524dfc16372c0b0b0c7327bb2d..a8adedd1bc17563aee013aef3f4bc76a0827b14f 100644 (file)
--- a/riscv/insns/mul_d.h
+++ b/riscv/insns/mul_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_d_rm.h b/riscv/insns/mul_d_rm.h
deleted file mode 100644 (file)
index a8adedd..0000000
--- a/riscv/insns/mul_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mul(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
index 3a5905bf47a2c53d26d1e85f8737b67128b67b7d..64755785991ec37d191962fc65975c854397a8ee 100644 (file)
--- a/riscv/insns/mul_s.h
+++ b/riscv/insns/mul_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_s_rm.h b/riscv/insns/mul_s_rm.h
deleted file mode 100644 (file)
index 6475578..0000000
--- a/riscv/insns/mul_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mul(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/nmadd_d.h
index 3d6ac527722db794299e7524851d498ac1e5fd91..1e2ee27a89db1a1a8bea846415e4fa07b341bfc9 100644 (file)
--- a/riscv/insns/nmadd_d.h
+++ b/riscv/insns/nmadd_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmadd_d_rm.h b/riscv/insns/nmadd_d_rm.h
deleted file mode 100644 (file)
index 1e2ee27..0000000
--- a/riscv/insns/nmadd_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
-set_fp_exceptions;

diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/nmadd_s.h
index aa05b5098d1f520e22fd8fe02ab1129977c041f5..78abb78f11fc73a28eabf8d0d2da06e17f3dfa19 100644 (file)
--- a/riscv/insns/nmadd_s.h
+++ b/riscv/insns/nmadd_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmadd_s_rm.h b/riscv/insns/nmadd_s_rm.h
deleted file mode 100644 (file)
index 78abb78..0000000
--- a/riscv/insns/nmadd_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
-set_fp_exceptions;

diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h
index fa4a862bb002567ee66e16195079adfc0417816d..ae643a56be09b037b110d4e62096689a54b0edbb 100644 (file)
--- a/riscv/insns/nmsub_d.h
+++ b/riscv/insns/nmsub_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_d_rm.h b/riscv/insns/nmsub_d_rm.h
deleted file mode 100644 (file)
index ae643a5..0000000
--- a/riscv/insns/nmsub_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
-set_fp_exceptions;

diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/nmsub_s.h
index 98442f84364d57889d942fd0d8eadc7aed1aa6e2..cbb70ba35d7ad64f30afeed8c4d70a10ff308a89 100644 (file)
--- a/riscv/insns/nmsub_s.h
+++ b/riscv/insns/nmsub_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_s_rm.h b/riscv/insns/nmsub_s_rm.h
deleted file mode 100644 (file)
index cbb70ba..0000000
--- a/riscv/insns/nmsub_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
-set_fp_exceptions;

diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h
index e2a2014007210c23827cbbbc0ec74fe4fafff001..7647c9c8d630f0dcf2b075998e3c881cbe241c28 100644 (file)
--- a/riscv/insns/sqrt_d.h
+++ b/riscv/insns/sqrt_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_d_rm.h b/riscv/insns/sqrt_d_rm.h
deleted file mode 100644 (file)
index 7647c9c..0000000
--- a/riscv/insns/sqrt_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_sqrt(FRS1);
-set_fp_exceptions;

diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h
index c491649a62333238e0c905c9bafd77995f30f270..426f24171118de816f72a09c0ce16ef88d747c33 100644 (file)
--- a/riscv/insns/sqrt_s.h
+++ b/riscv/insns/sqrt_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_s_rm.h b/riscv/insns/sqrt_s_rm.h
deleted file mode 100644 (file)
index 426f241..0000000
--- a/riscv/insns/sqrt_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_sqrt(FRS1);
-set_fp_exceptions;

diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h
index 54630a278a92531177899ff293c4a29214e93e60..e25eebbdc281b86f4d5aad2974dfcee16be4789a 100644 (file)
--- a/riscv/insns/sub_d.h
+++ b/riscv/insns/sub_d.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f64_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_d_rm.h b/riscv/insns/sub_d_rm.h
deleted file mode 100644 (file)
index e25eebb..0000000
--- a/riscv/insns/sub_d_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_sub(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
index 142c7ab6e557b254d3429f3b39b8ee6f78aa6c40..6c64d0435dff9f28e99c7d2d8dfec0c34a0e7674 100644 (file)
--- a/riscv/insns/sub_s.h
+++ b/riscv/insns/sub_s.h
@@ -1,3 +1,4 @@
 require_fp;
+softfloat_roundingMode = RM;
 FRD = f32_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_s_rm.h b/riscv/insns/sub_s_rm.h
deleted file mode 100644 (file)
index 6c64d04..0000000
--- a/riscv/insns/sub_s_rm.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_sub(FRS1, FRS2);
-set_fp_exceptions;

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 684f95df930e65303e5a3080c48f4a87e16691da..eed85da76154cadabd27b04d0ba6b88bf455df8d 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -59,7 +59,6 @@ void processor_t::set_sr(uint32_t val)
 void processor_t::set_fsr(uint32_t val)
 {
   fsr = val & ~FSR_ZERO;
-  softfloat_roundingMode = (fsr & FSR_RD) >> FSR_RD_SHIFT;
 }
 
 void processor_t::step(size_t n, bool noisy)