)
)
self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)
+
+class _TB(Module):
+ def __init__(self, test_seq_it):
+ self.test_seq_it = test_seq_it
+
+ self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
+ self.comb += self.chansync.valid_i.eq(1)
+
+ def do_simulation(self, selfp):
+ try:
+ de0, de1, de2 = next(self.test_seq_it)
+ except StopIteration:
+ raise StopSimulation
+
+ selfp.chansync.data_in0.de = de0
+ selfp.chansync.data_in1.de = de1
+ selfp.chansync.data_in2.de = de2
+ selfp.chansync.data_in0.d = selfp.simulator.cycle_counter
+ selfp.chansync.data_in1.d = selfp.simulator.cycle_counter
+ selfp.chansync.data_in2.d = selfp.simulator.cycle_counter
+
+ out0 = selfp.chansync.data_out0.d
+ out1 = selfp.chansync.data_out1.d
+ out2 = selfp.chansync.data_out2.d
+
+ print("{0:5} {1:5} {2:5}".format(out0, out1, out2))
+
+if __name__ == "__main__":
+ from migen.sim.generic import run_simulation
+
+ test_seq = [
+ (1, 1, 1),
+ (1, 1, 0),
+ (0, 0, 0),
+ (0, 0, 0),
+ (0, 0, 1),
+ (1, 1, 1),
+ (1, 1, 1),
+ ]
+ tb = _TB(iter(test_seq*2))
+ run_simulation(tb)
self.submodules.dut = Encoder()
self.comb += self.dut.de.eq(1)
- def do_simulation(self, s):
+ def do_simulation(self, selfp):
if self._end_cycle is None:
try:
nv = next(self._iter_inputs)
except StopIteration:
- self._end_cycle = s.cycle_counter + 4
+ self._end_cycle = selfp.simulator.cycle_counter + 4
else:
- s.wr(self.dut.d, nv)
- if s.cycle_counter == self._end_cycle:
- s.interrupt = True
- if s.cycle_counter > 4:
- self.outs.append(s.rd(self.dut.out))
+ selfp.dut.d = nv
+ if selfp.simulator.cycle_counter == self._end_cycle:
+ raise StopSimulation
+ if selfp.simulator.cycle_counter > 4:
+ self.outs.append(selfp.dut.out)
def _bit(i, n):
return (i >> n) & 1
return de, hsync, vsync, value
if __name__ == "__main__":
- from migen.sim.generic import Simulator
+ from migen.sim.generic import run_simulation
from random import Random
rng = Random(788)
test_list = [rng.randrange(256) for i in range(500)]
tb = _EncoderTB(test_list)
- Simulator(tb).run()
+ run_simulation(tb)
check = [_decode_tmds(out)[3] for out in tb.outs]
assert(check == test_list)
--- /dev/null
+from migen.fhdl.std import *
+from migen.bus.lasmibus import *
+from migen.sim.generic import run_simulation
+
+from misoclib.lasmicon.bankmachine import *
+
+from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
+
+def my_generator():
+ for x in range(10):
+ yield True, x
+ for x in range(10):
+ yield False, 128*x
+
+class TB(Module):
+ def __init__(self):
+ self.req = Interface(32, 32, 1,
+ sdram_timing.req_queue_size, sdram_phy.read_latency, sdram_phy.write_latency)
+ self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
+ self.submodules.logger = CommandLogger(self.dut.cmd, True)
+ self.generator = my_generator()
+ self.dat_ack_cnt = 0
+
+ def do_simulation(self, selfp):
+ if selfp.req.dat_ack:
+ self.dat_ack_cnt += 1
+ if selfp.req.req_ack:
+ try:
+ we, adr = next(self.generator)
+ except StopIteration:
+ selfp.req.stb = 0
+ if not selfp.req.lock:
+ print("data ack count: {0}".format(self.dat_ack_cnt))
+ raise StopSimulation
+ return
+ selfp.req.adr = adr
+ selfp.req.we = we
+ selfp.req.stb = 1
+
+if __name__ == "__main__":
+ run_simulation(TB(), vcd_name="my.vcd")
--- /dev/null
+from fractions import Fraction
+from math import ceil
+
+from migen.fhdl.std import *
+
+from misoclib import lasmicon
+
+MHz = 1000000
+clk_freq = (83 + Fraction(1, 3))*MHz
+
+clk_period_ns = 1000000000/clk_freq
+def ns(t, margin=True):
+ if margin:
+ t += clk_period_ns/2
+ return ceil(t/clk_period_ns)
+
+sdram_phy = lasmicon.PhySettings(
+ memtype="DDR",
+ dfi_d=64,
+ nphases=2,
+ rdphase=0,
+ wrphase=1,
+ rdcmdphase=1,
+ wrcmdphase=0,
+ cl=3,
+ read_latency=5,
+ write_latency=0
+)
+
+sdram_geom = lasmicon.GeomSettings(
+ bank_a=2,
+ row_a=13,
+ col_a=10
+)
+sdram_timing = lasmicon.TimingSettings(
+ tRP=ns(15),
+ tRCD=ns(15),
+ tWR=ns(15),
+ tWTR=2,
+ tREFI=ns(7800, False),
+ tRFC=ns(70),
+
+ req_queue_size=8,
+ read_time=32,
+ write_time=16
+)
+
+def decode_sdram(ras_n, cas_n, we_n, bank, address):
+ elts = []
+ if not ras_n and cas_n and we_n:
+ elts.append("ACTIVATE")
+ elts.append("BANK " + str(bank))
+ elts.append("ROW " + str(address))
+ elif ras_n and not cas_n and we_n:
+ elts.append("READ\t")
+ elts.append("BANK " + str(bank))
+ elts.append("COL " + str(address))
+ elif ras_n and not cas_n and not we_n:
+ elts.append("WRITE\t")
+ elts.append("BANK " + str(bank))
+ elts.append("COL " + str(address))
+ elif ras_n and cas_n and not we_n:
+ elts.append("BST")
+ elif not ras_n and not cas_n and we_n:
+ elts.append("AUTO REFRESH")
+ elif not ras_n and cas_n and not we_n:
+ elts.append("PRECHARGE")
+ if address & 2**10:
+ elts.append("ALL")
+ else:
+ elts.append("BANK " + str(bank))
+ elif not ras_n and not cas_n and not we_n:
+ elts.append("LMR")
+ return elts
+
+class CommandLogger(Module):
+ def __init__(self, cmd, rw=False):
+ self.cmd = cmd
+ if rw:
+ self.comb += self.cmd.ack.eq(1)
+
+ def do_simulation(self, selfp):
+ elts = ["@" + str(selfp.simulator.cycle_counter)]
+ cmdp = selfp.cmd
+ elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
+ if len(elts) > 1:
+ print("\t".join(elts))
+ do_simulation.passive = True
+
+class DFILogger(Module):
+ def __init__(self, dfi):
+ self.dfi = dfi
+
+ def do_simulation(self, selfp):
+ dfip = selfp.dfi
+ for i, p in enumerate(dfip.phases):
+ elts = ["@" + str(selfp.simulator.cycle_counter) + ":" + str(i)]
+ elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
+ if len(elts) > 1:
+ print("\t".join(elts))
+ do_simulation.passive = True
--- /dev/null
+from migen.fhdl.std import *
+from migen.bus.lasmibus import *
+from migen.sim.generic import run_simulation
+
+from misoclib.lasmicon import *
+
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+
+def my_generator_r(n):
+ for x in range(10):
+ t = TRead(128*n + 48*n*x)
+ yield t
+ print("{0:3}: reads done".format(n))
+
+def my_generator_w(n):
+ for x in range(10):
+ t = TWrite(128*n + 48*n*x, x)
+ yield t
+ print("{0:3}: writes done".format(n))
+
+def my_generator(n):
+ if n % 2:
+ return my_generator_w(n // 2)
+ else:
+ return my_generator_r(n // 2)
+
+class TB(Module):
+ def __init__(self):
+ self.submodules.dut = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
+ self.submodules.xbar = lasmibus.Crossbar([self.dut.lasmic], self.dut.nrowbits)
+ self.submodules.logger = DFILogger(self.dut.dfi)
+
+ masters = [self.xbar.get_master() for i in range(6)]
+ self.initiators = [Initiator(my_generator(n), master)
+ for n, master in enumerate(masters)]
+ self.submodules += self.initiators
+
+if __name__ == "__main__":
+ run_simulation(TB(), vcd_name="my.vcd")
--- /dev/null
+from migen.fhdl.std import *
+from migen.bus import lasmibus
+from migen.actorlib import dma_lasmi
+from migen.sim.generic import run_simulation
+
+from misoclib.lasmicon import *
+
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+
+class TB(Module):
+ def __init__(self):
+ self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
+ self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
+ self.submodules.logger = DFILogger(self.ctler.dfi)
+ self.submodules.writer = dma_lasmi.Writer(self.xbar.get_master())
+
+ self.comb += self.writer.address_data.stb.eq(1)
+ pl = self.writer.address_data.payload
+ pl.a.reset = 255
+ pl.d.reset = pl.a.reset*2
+ self.sync += If(self.writer.address_data.ack,
+ pl.a.eq(pl.a + 1),
+ pl.d.eq(pl.d + 2)
+ )
+ self.open_row = None
+
+ def do_simulation(self, selfp):
+ dfip = selfp.ctler.dfi
+ for p in dfip.phases:
+ if p.ras_n and not p.cas_n and not p.we_n: # write
+ d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
+ print(d)
+ if d != p.address//2 + p.bank*512 + self.open_row*2048:
+ print("**** ERROR ****")
+ elif not p.ras_n and p.cas_n and p.we_n: # activate
+ self.open_row = p.address
+
+if __name__ == "__main__":
+ run_simulation(TB(), ncycles=3500, vcd_name="my.vcd")
--- /dev/null
+from migen.fhdl.std import *
+from migen.bus import wishbone, wishbone2lasmi, lasmibus
+from migen.bus.transactions import *
+from migen.sim.generic import run_simulation
+
+from misoclib.lasmicon import *
+
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+
+l2_size = 8192 # in bytes
+
+def my_generator():
+ for x in range(20):
+ t = TWrite(x, x)
+ yield t
+ print(str(t) + " delay=" + str(t.latency))
+ for x in range(20):
+ t = TRead(x)
+ yield t
+ print(str(t) + " delay=" + str(t.latency))
+ for x in range(20):
+ t = TRead(x+l2_size//4)
+ yield t
+ print(str(t) + " delay=" + str(t.latency))
+
+class TB(Module):
+ def __init__(self):
+ self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
+ self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
+ self.submodules.logger = DFILogger(self.ctler.dfi)
+ self.submodules.bridge = wishbone2lasmi.WB2LASMI(l2_size//4, self.xbar.get_master())
+ self.submodules.initiator = wishbone.Initiator(my_generator())
+ self.submodules.conn = wishbone.InterconnectPointToPoint(self.initiator.bus, self.bridge.wishbone)
+
+if __name__ == "__main__":
+ run_simulation(TB(), vcd_name="my.vcd")
--- /dev/null
+from random import Random
+
+from migen.fhdl.std import *
+from migen.sim.generic import run_simulation
+
+from misoclib.lasmicon.refresher import *
+
+from common import CommandLogger
+
+class Granter(Module):
+ def __init__(self, req, ack):
+ self.req = req
+ self.ack = ack
+ self.state = 0
+ self.prng = Random(92837)
+
+ def do_simulation(self, selfp):
+ elts = ["@" + str(selfp.simulator.cycle_counter)]
+
+ if self.state == 0:
+ if selfp.req:
+ elts.append("Refresher requested access")
+ self.state = 1
+ elif self.state == 1:
+ if self.prng.randrange(0, 5) == 0:
+ elts.append("Granted access to refresher")
+ selfp.ack = 1
+ self.state = 2
+ elif self.state == 2:
+ if not selfp.req:
+ elts.append("Refresher released access")
+ selfp.ack = 0
+ self.state = 0
+
+ if len(elts) > 1:
+ print("\t".join(elts))
+
+class TB(Module):
+ def __init__(self):
+ self.submodules.dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
+ self.submodules.logger = CommandLogger(self.dut.cmd)
+ self.submodules.granter = Granter(self.dut.req, self.dut.ack)
+
+if __name__ == "__main__":
+ run_simulation(TB(), ncycles=400)
self.o.eq(Cat(*curval))
]
-def _print_lfsr_code():
- from migen.fhdl import verilog
- dut = LFSR(3, 4, [3, 2])
- print(verilog.convert(dut, ios={dut.ce, dut.reset, dut.o}))
-
-class _LFSRTB(Module):
- def __init__(self, *args, **kwargs):
- self.submodules.lfsr = LFSR(*args, **kwargs)
- self.comb += self.lfsr.ce.eq(1)
-
- def do_simulation(self, s):
- print("{0:032x}".format(s.rd(self.lfsr.o)))
-
-def _sim_lfsr():
- from migen.sim.generic import Simulator
- tb = _LFSRTB(128)
- sim = Simulator(tb)
- sim.run(20)
-
memtest_magic = 0x361f
class MemtestWriter(Module):
def get_csrs(self):
return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs()
+class _LFSRTB(Module):
+ def __init__(self, *args, **kwargs):
+ self.submodules.dut = LFSR(*args, **kwargs)
+ self.comb += self.dut.ce.eq(1)
+
+ def do_simulation(self, selfp):
+ print("{0:032x}".format(selfp.dut.o))
+
if __name__ == "__main__":
- _print_lfsr_code()
- _sim_lfsr()
+ from migen.fhdl import verilog
+ from migen.sim.generic import run_simulation
+
+ lfsr = LFSR(3, 4, [3, 2])
+ print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))
+
+ run_simulation(_LFSRTB(128), ncycles=20)
from migen.genlib.misc import timeline
from migen.genlib.record import Record
-
class SpiFlash(Module):
def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,
dummy=15, div=2):
self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
-
-
class SpiFlashTB(Module):
def __init__(self):
self.submodules.master = wishbone.Initiator(self.gen_reads())
yield t
print("read {} in {} cycles(s)".format(t.data, t.latency))
- def do_simulation(self, s):
- if s.rd(self.pads.cs_n):
+ def do_simulation(self, selfp):
+ if selfp.pads.cs_n:
self.cycle = 0
else:
self.cycle += 1
- if not s.rd(self.slave.dq.oe):
- s.wr(self.slave.dq.i, self.cycle & 0xf)
- s.interrupt = self.master.done
-
+ if not selfp.slave.dq.oe:
+ selfp.slave.dq.i = self.cycle & 0xf
+ do_simulation.passive = True
-def _main():
- from migen.sim.generic import Simulator, TopLevel
+if __name__ == "__main__":
+ from migen.sim.generic import run_simulation
from migen.fhdl import verilog
pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))
- tb = SpiFlashTB()
- sim = Simulator(tb, TopLevel("spiflash.vcd"))
- sim.run()
-
-
-if __name__ == "__main__":
- _main()
+ run_simulation(SpiFlashTB(), vcd_name="spiflash.vcd")
from migen.fhdl.std import *
from migen.genlib.fsm import *
+from migen.sim.generic import run_simulation
class Chopper(Module):
def __init__(self, N, frac_bits):
def __init__(self):
self.submodules.dut = Chopper(4, 16)
- def gen_simulation(self, s):
- from migen.sim.generic import Proxy
- dut = Proxy(s, self.dut)
+ def gen_simulation(self, selfp):
+ dut = selfp.dut
dut.init = 1
dut.p = 320
print("Ones: {} (expected: {})".format(ones, dut.p*niter*4//dut.q))
if __name__ == "__main__":
- from migen.sim.generic import Simulator
- with Simulator(_ChopperTB()) as s:
- s.run(1000)
+ run_simulation(_ChopperTB())
+++ /dev/null
-from migen.fhdl.std import *
-from migen.sim.generic import *
-
-from misoclib.dvisampler.chansync import ChanSync
-
-class TB(Module):
- def __init__(self, test_seq_it):
- self.test_seq_it = test_seq_it
-
- self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
- self.comb += self.chansync.valid_i.eq(1)
-
- def do_simulation(self, s):
- try:
- de0, de1, de2 = next(self.test_seq_it)
- except StopIteration:
- s.interrupt = True
- return
-
- s.wr(self.chansync.data_in0.de, de0)
- s.wr(self.chansync.data_in1.de, de1)
- s.wr(self.chansync.data_in2.de, de2)
- s.wr(self.chansync.data_in0.d, s.cycle_counter)
- s.wr(self.chansync.data_in1.d, s.cycle_counter)
- s.wr(self.chansync.data_in2.d, s.cycle_counter)
-
- out0 = s.rd(self.chansync.data_out0.d)
- out1 = s.rd(self.chansync.data_out1.d)
- out2 = s.rd(self.chansync.data_out2.d)
-
- print("{0:5} {1:5} {2:5}".format(out0, out1, out2))
-
-def main():
- test_seq = [
- (1, 1, 1),
- (1, 1, 0),
- (0, 0, 0),
- (0, 0, 0),
- (0, 0, 1),
- (1, 1, 1),
- (1, 1, 1),
- ]
- tb = TB(iter(test_seq*2))
- Simulator(tb).run()
-
-main()
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import asmibus
-from migen.sim.generic import Simulator
-
-from misoclib.framebuffer import *
-
-def main():
- hub = asmibus.Hub(16, 128)
- port = hub.get_port()
- hub.finalize()
-
- dut = Framebuffer(1, port, True)
-
- fragment = hub.get_fragment() + dut.get_fragment()
- sim = Simulator(fragment)
-
- sim.run(1)
- def csr_w(addr, d):
- sim.wr(dut.bank.description[addr].field.storage, d)
-
- hres = 4
- vres = 4
-
- csr_w(1, hres) # hres
- csr_w(2, hres+3) # hsync_start
- csr_w(3, hres+5) # hsync_stop
- csr_w(4, hres+10) # hscan
- csr_w(5, vres) # vres
- csr_w(6, vres+3) # vsync_start
- csr_w(7, vres+5) # vsync_stop
- csr_w(8, vres+10) # vscan
- csr_w(10, hres*vres*4) # length
- csr_w(0, 1) # enable
-
- sim.run(1000)
-
-main()
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus.lasmibus import *
-from migen.sim.generic import Simulator, TopLevel
-
-from misoclib.lasmicon.bankmachine import *
-
-from common import sdram_geom, sdram_timing, CommandLogger
-
-def my_generator():
- for x in range(10):
- yield True, x
- for x in range(10):
- yield False, 128*x
-
-class TB(Module):
- def __init__(self):
- self.req = Interface(32, 32, 1,
- sdram_timing.req_queue_size, sdram_timing.read_latency, sdram_timing.write_latency)
- self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
- self.submodules.logger = CommandLogger(self.dut.cmd, True)
- self.generator = my_generator()
- self.dat_ack_cnt = 0
-
- def do_simulation(self, s):
- if s.rd(self.req.dat_ack):
- self.dat_ack_cnt += 1
- if s.rd(self.req.req_ack):
- try:
- we, adr = next(self.generator)
- except StopIteration:
- s.wr(self.req.stb, 0)
- if not s.rd(self.req.lock):
- s.interrupt = True
- print("data ack count: {0}".format(self.dat_ack_cnt))
- return
- s.wr(self.req.adr, adr)
- s.wr(self.req.we, we)
- s.wr(self.req.stb, 1)
-
-def main():
- sim = Simulator(TB(), TopLevel("my.vcd"))
- sim.run()
-
-main()
+++ /dev/null
-from fractions import Fraction
-from math import ceil
-
-from migen.fhdl.std import *
-from migen.sim.generic import Proxy
-
-from misoclib import lasmicon
-
-MHz = 1000000
-clk_freq = (83 + Fraction(1, 3))*MHz
-
-clk_period_ns = 1000000000/clk_freq
-def ns(t, margin=True):
- if margin:
- t += clk_period_ns/2
- return ceil(t/clk_period_ns)
-
-sdram_phy = lasmicon.PhySettings(
- memtype="DDR",
- dfi_d=64,
- nphases=2,
- rdphase=0,
- wrphase=1,
- rdcmdphase=1,
- wrcmdphase=0,
- cl=3,
- read_latency=5,
- write_latency=0
-)
-
-sdram_geom = lasmicon.GeomSettings(
- bank_a=2,
- row_a=13,
- col_a=10
-)
-sdram_timing = lasmicon.TimingSettings(
- tRP=ns(15),
- tRCD=ns(15),
- tWR=ns(15),
- tWTR=2,
- tREFI=ns(7800, False),
- tRFC=ns(70),
-
- req_queue_size=8,
- read_time=32,
- write_time=16
-)
-
-def decode_sdram(ras_n, cas_n, we_n, bank, address):
- elts = []
- if not ras_n and cas_n and we_n:
- elts.append("ACTIVATE")
- elts.append("BANK " + str(bank))
- elts.append("ROW " + str(address))
- elif ras_n and not cas_n and we_n:
- elts.append("READ\t")
- elts.append("BANK " + str(bank))
- elts.append("COL " + str(address))
- elif ras_n and not cas_n and not we_n:
- elts.append("WRITE\t")
- elts.append("BANK " + str(bank))
- elts.append("COL " + str(address))
- elif ras_n and cas_n and not we_n:
- elts.append("BST")
- elif not ras_n and not cas_n and we_n:
- elts.append("AUTO REFRESH")
- elif not ras_n and cas_n and not we_n:
- elts.append("PRECHARGE")
- if address & 2**10:
- elts.append("ALL")
- else:
- elts.append("BANK " + str(bank))
- elif not ras_n and not cas_n and not we_n:
- elts.append("LMR")
- return elts
-
-class CommandLogger(Module):
- def __init__(self, cmd, rw=False):
- self.cmd = cmd
- if rw:
- self.comb += self.cmd.ack.eq(1)
-
- def do_simulation(self, s):
- elts = ["@" + str(s.cycle_counter)]
- cmdp = Proxy(s, self.cmd)
- elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
- if len(elts) > 1:
- print("\t".join(elts))
-
-class DFILogger(Module):
- def __init__(self, dfi):
- self.dfi = dfi
-
- def do_simulation(self, s):
- dfip = Proxy(s, self.dfi)
-
- for i, p in enumerate(dfip.phases):
- elts = ["@" + str(s.cycle_counter) + ":" + str(i)]
- elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
- if len(elts) > 1:
- print("\t".join(elts))
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus.lasmibus import *
-from migen.sim.generic import Simulator, TopLevel
-
-from misoclib.lasmicon import *
-
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
-
-def my_generator_r(n):
- for x in range(10):
- t = TRead(128*n + 48*n*x)
- yield t
- print("{0:3}: reads done".format(n))
-
-def my_generator_w(n):
- for x in range(10):
- t = TWrite(128*n + 48*n*x, x)
- yield t
- print("{0:3}: writes done".format(n))
-
-def my_generator(n):
- if n % 2:
- return my_generator_w(n // 2)
- else:
- return my_generator_r(n // 2)
-
-class TB(Module):
- def __init__(self):
- self.submodules.dut = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
- self.submodules.xbar = lasmibus.Crossbar([self.dut.lasmic], self.dut.nrowbits)
- self.submodules.logger = DFILogger(self.dut.dfi)
-
- masters = [self.xbar.get_master() for i in range(6)]
- self.initiators = [Initiator(my_generator(n), master)
- for n, master in enumerate(masters)]
- self.submodules += self.initiators
-
- def do_simulation(self, s):
- s.interrupt = all(initiator.done for initiator in self.initiators)
-
-
-def main():
- sim = Simulator(TB(), TopLevel("my.vcd"))
- sim.run()
-
-main()
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import lasmibus
-from migen.actorlib import dma_lasmi
-from migen.sim.generic import Simulator, TopLevel, Proxy
-
-from misoclib.lasmicon import *
-
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
-
-class TB(Module):
- def __init__(self):
- self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
- self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
- self.xbar.get_master() # FIXME: remove dummy master
- self.submodules.logger = DFILogger(self.ctler.dfi)
- self.submodules.writer = dma_lasmi.Writer(self.xbar.get_master())
-
- self.comb += self.writer.address_data.stb.eq(1)
- pl = self.writer.address_data.payload
- pl.a.reset = 255
- pl.d.reset = pl.a.reset*2
- self.sync += If(self.writer.address_data.ack,
- pl.a.eq(pl.a + 1),
- pl.d.eq(pl.d + 2)
- )
- self.open_row = None
-
- def do_simulation(self, s):
- dfip = Proxy(s, self.ctler.dfi)
- for p in dfip.phases:
- if p.ras_n and not p.cas_n and not p.we_n: # write
- d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
- print(d)
- if d != p.address//2 + p.bank*512 + self.open_row*2048:
- print("**** ERROR ****")
- elif not p.ras_n and p.cas_n and p.we_n: # activate
- self.open_row = p.address
-
-def main():
- sim = Simulator(TB(), TopLevel("my.vcd"))
- sim.run(3500)
-
-main()
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone, wishbone2lasmi, lasmibus
-from migen.bus.transactions import *
-from migen.sim.generic import Simulator, TopLevel
-
-from misoclib.lasmicon import *
-
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
-
-l2_size = 8192 # in bytes
-
-def my_generator():
- for x in range(20):
- t = TWrite(x, x)
- yield t
- print(str(t) + " delay=" + str(t.latency))
- for x in range(20):
- t = TRead(x)
- yield t
- print(str(t) + " delay=" + str(t.latency))
- for x in range(20):
- t = TRead(x+l2_size//4)
- yield t
- print(str(t) + " delay=" + str(t.latency))
-
-class TB(Module):
- def __init__(self):
- self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
- self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
- self.xbar.get_master() # FIXME: remove dummy master
- self.submodules.logger = DFILogger(self.ctler.dfi)
- self.submodules.bridge = wishbone2lasmi.WB2LASMI(l2_size//4, self.xbar.get_master())
- self.submodules.initiator = wishbone.Initiator(my_generator())
- self.submodules.conn = wishbone.InterconnectPointToPoint(self.initiator.bus, self.bridge.wishbone)
-
- def do_simulation(self, s):
- s.interrupt = self.initiator.done
-
-def main():
- sim = Simulator(TB(), TopLevel("my.vcd"))
- sim.run()
-
-main()
+++ /dev/null
-from random import Random
-
-from migen.fhdl.std import *
-from migen.sim.generic import Simulator, TopLevel
-
-from misoclib.lasmicon.refresher import *
-
-from common import CommandLogger
-
-class Granter(Module):
- def __init__(self, req, ack):
- self.req = req
- self.ack = ack
- self.state = 0
- self.prng = Random(92837)
-
- def do_simulation(self, s):
- elts = ["@" + str(s.cycle_counter)]
-
- if self.state == 0:
- if s.rd(self.req):
- elts.append("Refresher requested access")
- self.state = 1
- elif self.state == 1:
- if self.prng.randrange(0, 5) == 0:
- elts.append("Granted access to refresher")
- s.wr(self.ack, 1)
- self.state = 2
- elif self.state == 2:
- if not s.rd(self.req):
- elts.append("Refresher released access")
- s.wr(self.ack, 0)
- self.state = 0
-
- if len(elts) > 1:
- print("\t".join(elts))
-
-class TB(Module):
- def __init__(self):
- self.submodules.dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
- self.submodules.logger = CommandLogger(self.dut.cmd)
- self.submodules.granter = Granter(self.dut.req, self.dut.ack)
-
-def main():
- Simulator(TB()).run(400)
-
-main()
+++ /dev/null
-SOURCES=tb_s6ddrphy.v ../../verilog/s6ddrphy/s6ddrphy.v \
- $(XILINX)/verilog/src/unisims/ODDR2.v \
- $(XILINX)/verilog/src/unisims/OSERDES2.v \
- $(XILINX)/verilog/src/unisims/ISERDES2.v \
- $(XILINX)/verilog/src/unisims/IOBUF.v \
- $(XILINX)/verilog/src/unisims/OBUFT.v \
- $(XILINX)/verilog/src/unisims/BUFPLL.v
-
-RM ?= rm -f
-
-all: tb_s6ddrphy
-
-isim: tb_s6ddrphy
- ./tb_s6ddrphy
-
-cversim: $(SOURCES)
- cver $(SOURCES)
-
-clean:
- $(RM) tb_s6ddrphy verilog.log s6ddrphy.vcd
-
-tb_s6ddrphy: $(SOURCES)
- iverilog -o tb_s6ddrphy $(SOURCES)
-
-.PHONY: all clean isim cversim
+++ /dev/null
-[timestart] 0
-[size] 1741 771
-[pos] -1 -1
-*-14.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] tb_s6ddrphy.
-[treeopen] tb_s6ddrphy.dut.
-[treeopen] tb_s6ddrphy.dut.gen_dq[0].
-@28
-tb_s6ddrphy.dut.sys_clk
-tb_s6ddrphy.dut.clk2x_270
-tb_s6ddrphy.dut.clk4x_wr
-tb_s6ddrphy.dut.clk4x_wr_strb
-@22
-tb_s6ddrphy.dut.dfi_address_p0[12:0]
-tb_s6ddrphy.dut.dfi_address_p1[12:0]
-@200
--
-@22
-tb_s6ddrphy.dut.sd_a[12:0]
-@28
-tb_s6ddrphy.dut.sd_clk_out_p
-@22
-tb_s6ddrphy.dut.sd_dm[3:0]
-tb_s6ddrphy.dut.sd_dq[31:0]
-tb_s6ddrphy.dut.sd_dqs[3:0]
-@200
--
-@28
-tb_s6ddrphy.dut.dfi_wrdata_en_p1
-@22
-tb_s6ddrphy.dut.dfi_wrdata_mask_p0[7:0]
-tb_s6ddrphy.dut.dfi_wrdata_mask_p1[7:0]
-tb_s6ddrphy.dut.dfi_wrdata_p0[63:0]
-tb_s6ddrphy.dut.dfi_wrdata_p1[63:0]
-@200
--
-@29
-tb_s6ddrphy.dut.dfi_rddata_en_p0
-@22
-tb_s6ddrphy.dut.dfi_rddata_w0[63:0]
-tb_s6ddrphy.dut.dfi_rddata_w1[63:0]
-@28
-tb_s6ddrphy.dut.dfi_rddata_valid_w0
-[pattern_trace] 1
-[pattern_trace] 0
+++ /dev/null
-`timescale 1ns / 1ps
-
-module tb_s6ddrphy();
-
-reg sys_clk = 1'b0;
-reg clk2x_270 = 1'b0;
-reg clk4x_wr = 1'b0;
-wire clk4x_wr_strb;
-wire clk4x_rd = clk4x_wr;
-wire clk4x_rd_strb = clk4x_wr_strb;
-
-initial begin
- while(1) begin
- sys_clk <= 1'b1;
- #6;
- sys_clk <= 1'b0;
- #6;
- end
-end
-
-initial begin
- #4.5;
- while(1) begin
- clk2x_270 <= 1'b1;
- #3;
- clk2x_270 <= 1'b0;
- #3;
- end
-end
-
-initial begin
- while(1) begin
- clk4x_wr <= 1'b1;
- #1.5;
- clk4x_wr <= 1'b0;
- #1.5;
- end
-end
-
-BUFPLL #(
- .DIVIDE(4)
-) bufpll (
- .PLLIN(clk4x_wr),
- .GCLK(sys_clk),
- .LOCKED(1'b1),
- .IOCLK(),
- .LOCK(),
- .SERDESSTROBE(clk4x_wr_strb)
-);
-
-reg [12:0] dfi_address_p0 = 0;
-reg [12:0] dfi_address_p1 = 0;
-
-reg dfi_wrdata_en_p0 = 0;
-reg [7:0] dfi_wrdata_mask_p0 = 0;
-reg [63:0] dfi_wrdata_p0 = 0;
-reg dfi_wrdata_en_p1 = 0;
-reg [7:0] dfi_wrdata_mask_p1 = 0;
-reg [63:0] dfi_wrdata_p1 = 0;
-
-reg dfi_rddata_en_p0 = 0;
-reg dfi_rddata_en_p1 = 0;
-
-wire [31:0] sd_dq;
-reg [31:0] dq_tb = 32'hzzzzzzzz;
-assign sd_dq = dq_tb;
-
-s6ddrphy #(
- .NUM_AD(13),
- .NUM_BA(2),
- .NUM_D(64)
-) dut (
- .sys_clk(sys_clk),
- .clk2x_270(clk2x_270),
- .clk4x_wr(clk4x_wr),
- .clk4x_wr_strb(clk4x_wr_strb),
- .clk4x_rd(clk4x_rd),
- .clk4x_rd_strb(clk4x_rd_strb),
-
- .sd_clk_out_p(),
- .sd_clk_out_n(),
-
- .dfi_address_p0(dfi_address_p0),
- .dfi_address_p1(dfi_address_p1),
- .sd_a(),
-
- .dfi_wrdata_en_p0(dfi_wrdata_en_p0),
- .dfi_wrdata_mask_p0(dfi_wrdata_mask_p0),
- .dfi_wrdata_p0(dfi_wrdata_p0),
- .dfi_wrdata_en_p1(dfi_wrdata_en_p1),
- .dfi_wrdata_mask_p1(dfi_wrdata_mask_p1),
- .dfi_wrdata_p1(dfi_wrdata_p1),
- .sd_dq(sd_dq),
- .sd_dm(),
- .sd_dqs(),
-
- .dfi_rddata_en_p0(dfi_rddata_en_p0),
- .dfi_rddata_en_p1(dfi_rddata_en_p1),
- .dfi_rddata_w0(),
- .dfi_rddata_w1(),
- .dfi_rddata_valid_w0(),
- .dfi_rddata_valid_w1()
-);
-
-`define TEST_SIMPLE_CMD
-`define TEST_WRITE
-`define TEST_READ
-
-initial begin
- $dumpfile("s6ddrphy.vcd");
- $dumpvars(3, dut);
-
-`ifdef TEST_SIMPLE_CMD
- #13;
- dfi_address_p0 <= 13'h1aba;
- dfi_address_p1 <= 13'h1234;
- #12;
- dfi_address_p0 <= 0;
- dfi_address_p1 <= 0;
- #59;
-`endif
-
-`ifdef TEST_WRITE
- #13;
- dfi_address_p1 <= 13'h0dbe;
- dfi_wrdata_en_p1 <= 1;
- dfi_wrdata_mask_p0 <= 8'h12;
- dfi_wrdata_mask_p1 <= 8'h34;
- dfi_wrdata_p0 <= 64'hcafebabeabadface;
- dfi_wrdata_p1 <= 64'h0123456789abcdef;
- #12;
- dfi_address_p1 <= 0;
- dfi_wrdata_en_p1 <= 0;
- dfi_wrdata_mask_p0 <= 0;
- dfi_wrdata_mask_p1 <= 0;
- dfi_wrdata_p0 <= 64'd0;
- dfi_wrdata_p1 <= 64'd0;
- #59;
-`endif
-
-`ifdef TEST_READ
- #13;
- dfi_address_p0 <= 13'h1234;
- dfi_rddata_en_p0 <= 1;
- #12;
- dfi_address_p0 <= 0;
- dfi_rddata_en_p0 <= 0;
- #15.5;
- dq_tb <= 32'h12345678;
- #3;
- dq_tb <= 32'hdeadbeef;
- #3;
- dq_tb <= 32'hcafebabe;
- #3;
- dq_tb <= 32'habadface;
- #3;
- dq_tb <= 32'hzzzzzzzz;
- #60;
-`endif
-
- $finish;
-end
-
-endmodule
-
-module glbl();
-wire GSR = 1'b0;
-wire GTS = 1'b0;
-endmodule
projects / litex.git / commitdiff