Change numerous occurrences of TARGET_POWERPC to ! TARGET_POWER and

make related changes.

From-SVN: r6199

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 55a09c5218fecc87354c0f363a1ce1c8960c0aaf..8bf5cd08ca6c80eb88d2d6caf990b994a8990f77 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -684,7 +684,7 @@
                             (match_operand:SI 2 "gpc_reg_operand" "r"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "mullw. %3,%1,%2"
   [(set_attr "type" "delayed_compare")])
 
@@ -707,7 +707,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (mult:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "mullw. %0,%1,%2"
   [(set_attr "type" "delayed_compare")])
 
@@ -755,11 +755,10 @@
       && exact_log2 (INTVAL (operands[2])) >= 0)
     ;
 
-  else if (TARGET_POWER)
+  else if (! TARGET_POWERPC)
     FAIL;
 
-  else if (TARGET_POWERPC)
-    operands[2] = force_reg (SImode, operands[2]);
+  operands[2] = force_reg (SImode, operands[2]);
 }")
 
 (define_expand "modsi3"
@@ -1560,7 +1559,7 @@
   if (TARGET_POWER)
     emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
   else
-    emit_insn (gen_ashlsi3_powerpc (operands[0], operands[1], operands[2]));
+    emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
   DONE;
 }")
 
@@ -1575,11 +1574,11 @@
    {sli|slwi} %0,%1,%h2"
   [(set_attr "length" "8")])
 
-(define_insn "ashlsi3_powerpc"
+(define_insn "ashlsi3_no_power"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "slw%I2 %0,%1,%2"
   [(set_attr "length" "8")])
 
@@ -1595,6 +1594,7 @@
    sle. %3,%1,%2
    {sli.|slwi.} %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
+
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -1618,6 +1618,7 @@
    sle. %0,%1,%2
    {sli.|slwi.} %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
+
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -1674,7 +1675,7 @@
   if (TARGET_POWER)
     emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
   else
-    emit_insn (gen_lshrsi3_powerpc (operands[0], operands[1], operands[2]));
+    emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
   DONE;
 }")
 
@@ -1688,11 +1689,11 @@
   sre %0,%1,%2
   {s%A2i|s%A2wi} %0,%1,%h2")
 
-(define_insn "lshrsi3_powerpc"
+(define_insn "lshrsi3_no_power"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "srw%I2 %0,%1,%2")
 
 (define_insn ""
@@ -1714,7 +1715,7 @@
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "srw%I2. %3,%1,%2"
   [(set_attr "type" "delayed_compare")])
 
@@ -1739,7 +1740,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "srw%I2. %0,%1,%2"
   [(set_attr "type" "delayed_compare")])
 
@@ -1886,7 +1887,7 @@
   if (TARGET_POWER)
     emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
   else
-    emit_insn (gen_ashrsi3_powerpc (operands[0], operands[1], operands[2]));
+    emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
   DONE;
 }")
 
@@ -1900,11 +1901,11 @@
    srea %0,%1,%2
    {srai|srawi} %0,%1,%h2")
 
-(define_insn "ashrsi3_powerpc"
+(define_insn "ashrsi3_no_power"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "sraw%I2 %0,%1,%2")
 
 (define_insn ""
@@ -1926,7 +1927,7 @@
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "sraw%I2. %3,%1,%2"
   [(set_attr "type" "delayed_compare")])
 
@@ -1951,7 +1952,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "sraw%I2. %0,%1,%2"
   [(set_attr "type" "delayed_compare")])
 
@@ -1964,7 +1965,7 @@
   if (TARGET_POWER)
     emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
   else
-    emit_insn (gen_extendqisi2_powerpc (operands[0], operands[1]));
+    emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
   DONE;
 }")
 
@@ -1982,14 +1983,14 @@
 { operands[1] = gen_lowpart (SImode, operands[1]);
   operands[2] = gen_reg_rtx (SImode); }")
 
-(define_expand "extendqisi2_powerpc"
+(define_expand "extendqisi2_no_power"
   [(set (match_dup 2)
                   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
                              (const_int 24)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
                   (ashiftrt:SI (match_dup 2)
                                (const_int 24)))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "
 { operands[1] = gen_lowpart (SImode, operands[1]);
   operands[2] = gen_reg_rtx (SImode); }")
@@ -2003,7 +2004,7 @@
   if (TARGET_POWER)
     emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
   else
-    emit_insn (gen_extendqihi2_powerpc (operands[0], operands[1]));
+    emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
   DONE;
 }")
 
@@ -2022,14 +2023,14 @@
   operands[1] = gen_lowpart (SImode, operands[1]);
   operands[2] = gen_reg_rtx (SImode); }")
 
-(define_expand "extendqihi2_powerpc"
+(define_expand "extendqihi2_no_power"
   [(set (match_dup 2)
                   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
                              (const_int 24)))
    (set (match_operand:HI 0 "gpc_reg_operand" "")
                   (ashiftrt:SI (match_dup 2)
                                (const_int 24)))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "
 { operands[0] = gen_lowpart (SImode, operands[0]);
   operands[1] = gen_lowpart (SImode, operands[1]);
@@ -2553,7 +2554,7 @@
   ""
   "
 {
-  if (TARGET_POWERPC
+  if (! TARGET_POWER
       && short_cint_operand (operands[2], DImode))
     FAIL;
 }")
@@ -2572,7 +2573,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "addc %L0,%L1,%L2\;adde %0,%1,%2"
   [(set_attr "length" "8")])
 
@@ -2583,7 +2584,7 @@
   ""
   "
 {
-  if (TARGET_POWERPC
+  if (! TARGET_POWER
       && short_cint_operand (operands[1], DImode))
     FAIL;
 }")
@@ -2602,7 +2603,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
                  (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC"
+  "! TARGET_POWER"
   "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
   [(set_attr "length" "8")])
 
@@ -2615,17 +2616,10 @@
 (define_insn ""
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
+  ""
   "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
   [(set_attr "length" "8")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-       (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC"
-  "subfic %L0,%L1,0\;subfze %0,%1"
-  [(set_attr "length" "8")])
-
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
@@ -2748,7 +2742,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
        (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))]
-  "TARGET_POWERPC && (gpc_reg_operand (operands[0], SImode)
+  "! TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
    || gpc_reg_operand (operands[1], SImode))"
   "@
    mr %0,%1
@@ -2826,7 +2820,7 @@
 (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
        (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
-  "TARGET_POWERPC && (gpc_reg_operand (operands[0], HImode)
+  "! TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
    || gpc_reg_operand (operands[1], HImode))"
   "@
    ori %0,%1,0
@@ -2874,7 +2868,7 @@
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
        (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
-  "TARGET_POWERPC && (gpc_reg_operand (operands[0], QImode)
+  "! TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
    || gpc_reg_operand (operands[1], QImode))"
   "@
    mr %0,%1