decorators: remove deprecated semantics

diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
index 723522042f3b9edbfc6996e5ad58733aeefc4715..79519d4a30ad0535cad9d749b897c52a8499fcf6 100644 (file)
--- a/examples/basic/two_dividers.py
+++ b/examples/basic/two_dividers.py
@@ -2,8 +2,8 @@ from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Example(Module):
        def __init__(self, width):
                d1 = divider.Divider(width)

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 4a044b8f2a7d98317aeed45bff2ac207c773cdff..548c3add93380448971884a75b4877bef3cbd62d 100644 (file)
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -158,7 +158,7 @@ class AsyncFIFO(Module, _FIFOInterface):
        """Asynchronous FIFO (first in, first out)
 
        Read and write interfaces are accessed from different clock domains,
-       named `read` and `write`. Use `RenameClockDomains` to rename to
+       named `read` and `write`. Use `ClockDomainsRenamer` to rename to
        other names.
 
        {interface}
@@ -172,8 +172,8 @@ class AsyncFIFO(Module, _FIFOInterface):
 
                depth_bits = log2_int(depth, True)
 
-               produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
-               consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
+               produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits+1))
+               consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits+1))
                self.submodules += produce, consume
                self.comb += [
                        produce.ce.eq(self.writable & self.we),

diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
index 8942ab0ba09872ca61d49760de7daf157160582e..b505032e86bb7853dacd6508f9c25ba51268c431 100644 (file)
--- a/migen/genlib/misc.py
+++ b/migen/genlib/misc.py
@@ -86,24 +86,24 @@ def timeline(trigger, events):
        sync.append(counterlogic)
        return sync
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class FlipFlop(Module):
        def __init__(self, *args, **kwargs):
                self.d = Signal(*args, **kwargs)
                self.q = Signal(*args, **kwargs)
                self.sync += self.q.eq(self.d)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Counter(Module):
        def __init__(self, *args, increment=1, **kwargs):
                self.value = Signal(*args, **kwargs)
                self.width = flen(self.value)
                self.sync += self.value.eq(self.value+increment)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Timeout(Module):
        def __init__(self, length):
                self.reached = Signal()