(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 312b4abb94eea3096abf1b8bc07408c20aa7e700..852b6b18ee9e2646e7e1a15cbf74ed8afa254004 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -602,7 +602,8 @@ multiplied by zero.  Thus, a sequence of LD operations will load from
 the exact same address, and likewise STs to the exact same address.
 
 Ordinarily this would make absolutely no sense whatsoever, except
-that Power ISA has cache-inhibited LD/STs, for accessing memory-mapped
+that Power ISA has cache-inhibited LD/STs (Power ISA v.1, Book III,
+1.6.1, p1033), for accessing memory-mapped
 peripherals and other crucial uses.  Thus, *despite not being a mapreduce mode*,
 zero-immediates cause multiple hits on the same element.