x86: Changes to decoder, corrects 9376

The changes made by the changeset 9376 were not quite correct. The patch made
changes to the code which resulted in decoder not getting initialized correctly
when the state was restored from a checkpoint.

This patch adds a startup function to each ISA object. For x86, this function
sets the required state in the decoder. For other ISAs, the function is empty
right now.

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 739b772866a1d159c814870e83d9716acf3f8fa8..1832f02229cffc13c3325e0fa25ce5ff4ec33c30 100644 (file)
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -106,6 +106,8 @@ namespace AlphaISA
         const Params *params() const;
 
         ISA(Params *p);
+
+        void startup(ThreadContext *tc) {}
     };
 }
 

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index f5fe5f83446010736f906b52ef7eb42433cf2c24..12ecc492127381951903309c3490474c7bf97710 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -193,6 +193,8 @@ namespace ArmISA
             updateRegMap(tmp_cpsr);
         }
 
+        void startup(ThreadContext *tc) {}
+
         typedef ArmISAParams Params;
 
         const Params *params() const;

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 2169c0de0de5d280d96341333f92227e7ad84f73..5ae779a6c4603fe06d3b7b98da51d8555cdb493a 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -157,6 +157,8 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        void startup(ThreadContext *tc) {}
+
         const Params *params() const;
 
         ISA(Params *p);

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index a989d33a75148952505f4b1a3fa9439f7acf6397..f4e053d853129ef74844c363ca3a25d276ba9de7 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -98,6 +98,8 @@ class ISA : public SimObject
         return reg;
     }
 
+    void startup(ThreadContext *tc) {}
+
     const Params *params() const;
 
     ISA(Params *p);

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 3dd9f610971c5d168f53b162eb9bf797dd787af7..dac8a20952584a6ceb0c41a5b915ade752147bf8 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -171,6 +171,8 @@ class ISA : public SimObject
 
     void unserialize(Checkpoint *cp, const std::string & section);
 
+    void startup(ThreadContext *tc) {}
+
   protected:
 
     bool isHyperPriv() { return hpstate.hpriv; }

diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 381dc59995302743ecf6dd028834f4612951a92c..f65bc2392c5a261ce9331abc1050372fbf4f85c7 100644 (file)
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -387,6 +387,12 @@ ISA::unserialize(Checkpoint * cp, const std::string & section)
                      NULL);
 }
 
+void
+ISA::startup(ThreadContext *tc)
+{
+    tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
+}
+
 }
 
 X86ISA::ISA *

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 7c5330ca383b143e1e0ea58cbd1acc79e30ae401..e87d747bca1b126802e9a1fc03d1f115422bd0f5 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -87,6 +87,7 @@ namespace X86ISA
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
+        void startup(ThreadContext *tc);
     };
 }
 

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 18c536090aaa0b9f66864683e90eb0c61f86830b..393b9a189d1245654ff6caadde652b6922fa0480 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -678,6 +678,9 @@ template <class Impl>
 void
 FullO3CPU<Impl>::startup()
 {
+    for (int tid = 0; tid < numThreads; ++tid)
+        isa[tid]->startup(threadContexts[tid]);
+
     fetch.startupStage();
     decode.startupStage();
     iew.startupStage();

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 13e08a6cb3e62134d4fcb0f12a94a06daaba49ee..4db1c6c10d520cf89f577725d25349b0b990e0d1 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -515,6 +515,13 @@ BaseSimpleCPU::advancePC(Fault fault)
     }
 }
 
+void
+BaseSimpleCPU::startup()
+{
+    BaseCPU::startup();
+    thread->startup();
+}
+
 /*Fault
 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
 {

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 18b97c42fce9096fcf33766cc33316e05d14c54d..7e84dcc163746b6d1358b01533192ccce380f467 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -172,6 +172,8 @@ class BaseSimpleCPU : public BaseCPU
     virtual void regStats();
     virtual void resetStats();
 
+    virtual void startup();
+
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 9cf8da7b4c28b1a7074f69c00e8efb9bc80a87ce..77569aa68d91ec3f71765045c095c2d28e1c046b 100644 (file)
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -142,6 +142,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     ::unserialize(*tc, cp, section);
 }
 
+void
+SimpleThread::startup()
+{
+    isa->startup(tc);
+}
+
 void
 SimpleThread::dumpFuncProfile()
 {

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 6f1173b7ff7fe4a4db141c8277f8e7e6e4b30303..d752ed105daae1af4f689baad465b9a0cd122c35 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -150,6 +150,7 @@ class SimpleThread : public ThreadState
 
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
+    void startup();
 
     /***************************************************************
      *  SimpleThread functions to provide CPU with access to various