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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 5e5ca12ca35811d8e0cb7c314b00efa8b7bca6f9..bc3eeb67731b6ff1be34bb582783fae63af30e49 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -605,10 +605,10 @@ out to an entirely different loop, all based on conditions determined
 dynamically at runtime.
 
 Even when deployed on as basic a CPU as a single-issue in-order RISC
-core, the performance and power-savings were astonishing: between 20
-and **80%** reduction in algorithm completion times were achieved compared
+core, the performance and power-savings were astonishing: between 27
+and **75%** reduction in algorithm completion times were achieved compared
 to a more traditional branch-speculative in-order RISC CPU.  MPEG
-Decode, the target algorithm specifically picked by the researcher
+Encode's timing, the target algorithm specifically picked by the researcher
 due to its high complexity with 6-deep nested loops and conditional
 execution that frequently jumped in and out of at least 2 loops,
 came out with an astonishing 43% improvement in completion time. 43%