whitespace

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 43776d23e4a5f677c558f1f5630a1811fcec01e7..2971f9dbec7cef15cdbf4e746d03815921198d57 100644 (file)
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -105,9 +105,11 @@ Book I as a new Section 4.6.2.1
 
 Pseudocode:
 
+```
     bf16 = d0 || d1 || d2 # create BF16 immediate
     fp32 = bf16 || [0]*16 # convert BF16 to FP32
     FRS = DOUBLE(fp32)    # convert FP32 to FP64
+```
 
 Special registers altered:
 
@@ -120,14 +122,14 @@ Reinterprets `D << 16` as a 32-bit float, which is then converted to a
 Examples:
 
 ```
-fmvis f4, 0 # writes +0.0 to f4 (clears an FPR)
-fmvis f4, 0x8000 # writes -0.0 to f4
-fmvis f4, 0x3F80 # writes +1.0 to f4
-fmvis f4, 0xBFC0 # writes -1.5 to f4
-fmvis f4, 0x7FC0 # writes +qNaN to f4
-fmvis f4, 0x7F80 # writes +Infinity to f4
-fmvis f4, 0xFF80 # writes -Infinity to f4
-fmvis f4, 0x3FFF # writes +1.9921875 to f4
+    fmvis f4, 0 # writes +0.0 to f4 (clears an FPR)
+    fmvis f4, 0x8000 # writes -0.0 to f4
+    fmvis f4, 0x3F80 # writes +1.0 to f4
+    fmvis f4, 0xBFC0 # writes -1.5 to f4
+    fmvis f4, 0x7FC0 # writes +qNaN to f4
+    fmvis f4, 0x7F80 # writes +Infinity to f4
+    fmvis f4, 0xFF80 # writes -Infinity to f4
+    fmvis f4, 0x3FFF # writes +1.9921875 to f4
 ```
 
 # Floating-Point Immediate Second-Half Move
@@ -142,10 +144,12 @@ DX-Form:
 
 Pseudocode:
 
+```
     n <- (FRS)                     # read FRS
     fp32 <- SINGLE(n)              # convert to FP32
     fp32[16:31] <- d0 || d1 || d2  # replace LSB half
     FRS <- DOUBLE(fp32)            # convert back to FP64
+```
 
 Special registers altered:
 
@@ -170,13 +174,13 @@ lower 16-bits.
 Example:
 
 ```
-# these two combined instructions write 0x3f808000
-# into f4 as an FP32 to be converted to an FP64.
-# actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
-# first the upper bits, happens to be +1.0
-fmvis f4, 0x3F80 # writes +1.0 to f4
-# now write the lower 16 bits of an FP32
-fishmv f4, 0x8000 # writes +1.00390625 to f4
+    # these two combined instructions write 0x3f808000
+    # into f4 as an FP32 to be converted to an FP64.
+    # actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
+    # first the upper bits, happens to be +1.0
+    fmvis f4, 0x3F80 # writes +1.0 to f4
+    # now write the lower 16 bits of an FP32
+    fishmv f4, 0x8000 # writes +1.00390625 to f4
 ```
 [[!tag opf_rfc]]