Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 2ab4a8c6e719f6844e442990e101ddad2bc67509..acfba057fdfea794565c6a9b2bbca6df38299ffb 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1324,6 +1324,13 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
        offset = 0;
 }
 
+RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
+{
+       this->wire = wire;
+       this->width = wire->width;
+       this->offset = 0;
+}
+
 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
 {
        this->wire = wire;
@@ -1331,6 +1338,15 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
        this->offset = offset;
 }
 
+RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width)
+{
+       RTLIL::SigChunk chunk;
+       chunk.wire = wire;
+       chunk.width = width;
+       chunk.offset = offset;
+       return chunk;
+}
+
 RTLIL::SigChunk::SigChunk(const std::string &str)
 {
        wire = NULL;
@@ -1432,6 +1448,13 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
        check();
 }
 
+RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
+{
+       chunks_.push_back(RTLIL::SigChunk(wire));
+       width_ = chunks_.back().width;
+       check();
+}
+
 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
 {
        chunks_.push_back(RTLIL::SigChunk(wire, width, offset));
@@ -1439,6 +1462,15 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
        check();
 }
 
+RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width)
+{
+       RTLIL::SigSpec sig;
+       sig.chunks_.push_back(RTLIL::SigChunk::grml(wire, offset, width));
+       sig.width_ = sig.chunks_.back().width;
+       sig.check();
+       return sig;
+}
+
 RTLIL::SigSpec::SigSpec(const std::string &str)
 {
        chunks_.push_back(RTLIL::SigChunk(str));

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 0e74c958aa193061e58a960a4715e9b8f6b57d20..542e685de34cd6f97460ee83e2762b2c1a648c39 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -462,7 +462,10 @@ struct RTLIL::SigChunk {
        int width, offset;
        SigChunk();
        SigChunk(const RTLIL::Const &value);
-       SigChunk(RTLIL::Wire *wire, int width, int offset);
+       SigChunk(RTLIL::Wire *wire);
+       SigChunk(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
+       SigChunk(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
+       static SigChunk grml(RTLIL::Wire *wire, int offset, int width = 1);
        SigChunk(const std::string &str);
        SigChunk(int val, int width = 32);
        SigChunk(RTLIL::State bit, int width = 1);
@@ -522,7 +525,10 @@ public:
        SigSpec();
        SigSpec(const RTLIL::Const &value);
        SigSpec(const RTLIL::SigChunk &chunk);
-       SigSpec(RTLIL::Wire *wire, int width = -1, int offset = 0);
+       SigSpec(RTLIL::Wire *wire);
+       SigSpec(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
+       SigSpec(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
+       static SigSpec grml(RTLIL::Wire *wire, int offset, int width = 1);
        SigSpec(const std::string &str);
        SigSpec(int val, int width = 32);
        SigSpec(RTLIL::State bit, int width = 1);

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 2d921b7bec877756eeae4100753f3e7d354b41c1..e7371ec526668215bc6835ddf446326df9d0db37 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                        clk_str = clk_str.substr(1);
                }
                if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
-                       clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1));
+                       clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0));
        }
 
        if (dff_mode && clk_sig.size() == 0)

diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 738b0bd6d5e69ca5dbb750b9c7aee30e80ad9fe9..724bc3f985152ee67aa407fd85376662042a1d31 100644 (file)
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -292,8 +292,8 @@ struct ShareWorker
                        supercell->connections["\\Y"] = y;
                        module->add(supercell);
 
-                       RTLIL::SigSpec new_y1(y, y1.size());
-                       RTLIL::SigSpec new_y2(y, y2.size());
+                       RTLIL::SigSpec new_y1(y, y1.size(), 0);
+                       RTLIL::SigSpec new_y2(y, y2.size(), 0);
 
                        module->connections.push_back(RTLIL::SigSig(y1, new_y1));
                        module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -405,8 +405,8 @@ struct ShareWorker
                        supercell->connections["\\Y"] = y;
                        supercell->check();
 
-                       RTLIL::SigSpec new_y1(y, y1.size());
-                       RTLIL::SigSpec new_y2(y, y2.size());
+                       RTLIL::SigSpec new_y1(y, y1.size(), 0);
+                       RTLIL::SigSpec new_y2(y, y2.size(), 0);
 
                        module->connections.push_back(RTLIL::SigSig(y1, new_y1));
                        module->connections.push_back(RTLIL::SigSig(y2, new_y2));