ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
- return isa->getCurSveVecLenInBits(tc);
+ return isa->getCurSveVecLenInBits();
}
}
return dynamic_cast<const Params *>(_params);
}
-void
-ISA::clear(ThreadContext *tc)
-{
- clear();
- // Invalidate cached copies of miscregs in the TLBs
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
-}
-
void
ISA::clear()
{
const Params *p(params());
+ // Invalidate cached copies of miscregs in the TLBs
+ if (tc) {
+ getITBPtr(tc)->invalidateMiscReg();
+ getDTBPtr(tc)->invalidateMiscReg();
+ }
+
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
memset(miscRegs, 0, sizeof(miscRegs));
}
void
-ISA::startup(ThreadContext *tc)
+ISA::startup()
{
- pmu->setThreadContext(tc);
+ BaseISA::startup();
- if (system) {
- Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
- if (gicv3) {
- gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
- gicv3CpuInterface->setISA(this);
- gicv3CpuInterface->setThreadContext(tc);
- }
- }
+ if (tc)
+ setupThreadContext();
afterStartup = true;
}
void
-ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
+ISA::setupThreadContext()
{
- pmu->setThreadContext(new_tc);
+ pmu->setThreadContext(tc);
- if (system && gicv3CpuInterface) {
- gicv3CpuInterface->setISA(this);
- gicv3CpuInterface->setThreadContext(new_tc);
- }
+ if (!system)
+ return;
+
+ Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
+ if (!gicv3)
+ return;
+
+ if (!gicv3CpuInterface)
+ gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+ gicv3CpuInterface->setISA(this);
+ gicv3CpuInterface->setThreadContext(tc);
+}
+
+void
+ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
+{
+ tc = new_tc;
+ setupThreadContext();
}
RegVal
RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+ISA::readMiscReg(int misc_reg)
{
CPSR cpsr = 0;
PCState pc = 0;
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
- return getGenericTimer(tc).readMiscReg(misc_reg);
+ return getGenericTimer().readMiscReg(misc_reg);
case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
- return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
+ return getGICv3CPUInterface().readMiscReg(misc_reg);
default:
break;
}
void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val)
{
RegVal newVal = val;
pc.nextJazelle(cpsr.j);
pc.illegalExec(cpsr.il == 1);
- tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1);
+ tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
// Follow slightly different semantics if a CheckerCPU object
// is connected
// TLB Invalidate All
case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
tlbiOp(tc);
// TLB Invalidate All, Inner Shareable
case MISCREG_TLBIALLIS:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
tlbiOp.broadcast(tc);
// Instruction TLB Invalidate All
case MISCREG_ITLBIALL:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
tlbiOp(tc);
// Data TLB Invalidate All
case MISCREG_DTLBIALL:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
tlbiOp(tc);
case MISCREG_TLBIMVA:
case MISCREG_TLBIMVAL:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVA tlbiOp(EL1,
haveSecurity && !scr.ns,
case MISCREG_TLBIMVAIS:
case MISCREG_TLBIMVALIS:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVA tlbiOp(EL1,
haveSecurity && !scr.ns,
// TLB Invalidate by ASID match
case MISCREG_TLBIASID:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIASID tlbiOp(EL1,
haveSecurity && !scr.ns,
// TLB Invalidate by ASID match, Inner Shareable
case MISCREG_TLBIASIDIS:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIASID tlbiOp(EL1,
haveSecurity && !scr.ns,
case MISCREG_TLBIMVAA:
case MISCREG_TLBIMVAAL:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
mbits(newVal, 31,12));
case MISCREG_TLBIMVAAIS:
case MISCREG_TLBIMVAALIS:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
mbits(newVal, 31,12));
case MISCREG_TLBIMVAH:
case MISCREG_TLBIMVALH:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12));
case MISCREG_TLBIMVAHIS:
case MISCREG_TLBIMVALHIS:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12));
case MISCREG_TLBIIPAS2:
case MISCREG_TLBIIPAS2L:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIIPA tlbiOp(EL1,
haveSecurity && !scr.ns,
case MISCREG_TLBIIPAS2IS:
case MISCREG_TLBIIPAS2LIS:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
TLBIIPA tlbiOp(EL1,
haveSecurity && !scr.ns,
// Instruction TLB Invalidate by VA
case MISCREG_ITLBIMVA:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
ITLBIMVA tlbiOp(EL1,
haveSecurity && !scr.ns,
// Data TLB Invalidate by VA
case MISCREG_DTLBIMVA:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
DTLBIMVA tlbiOp(EL1,
haveSecurity && !scr.ns,
// Instruction TLB Invalidate by ASID match
case MISCREG_ITLBIASID:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
ITLBIASID tlbiOp(EL1,
haveSecurity && !scr.ns,
// Data TLB Invalidate by ASID match
case MISCREG_DTLBIASID:
{
- assert32(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert32();
+ scr = readMiscReg(MISCREG_SCR);
DTLBIASID tlbiOp(EL1,
haveSecurity && !scr.ns,
// TLB Invalidate All, Non-Secure Non-Hyp
case MISCREG_TLBIALLNSNH:
{
- assert32(tc);
+ assert32();
TLBIALLN tlbiOp(EL1);
tlbiOp(tc);
// TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
case MISCREG_TLBIALLNSNHIS:
{
- assert32(tc);
+ assert32();
TLBIALLN tlbiOp(EL1);
tlbiOp.broadcast(tc);
// TLB Invalidate All, Hyp mode
case MISCREG_TLBIALLH:
{
- assert32(tc);
+ assert32();
TLBIALLN tlbiOp(EL2);
tlbiOp(tc);
// TLB Invalidate All, Hyp mode, Inner Shareable
case MISCREG_TLBIALLHIS:
{
- assert32(tc);
+ assert32();
TLBIALLN tlbiOp(EL2);
tlbiOp.broadcast(tc);
// AArch64 TLB Invalidate All, EL3
case MISCREG_TLBI_ALLE3:
{
- assert64(tc);
+ assert64();
TLBIALL tlbiOp(EL3, true);
tlbiOp(tc);
// AArch64 TLB Invalidate All, EL3, Inner Shareable
case MISCREG_TLBI_ALLE3IS:
{
- assert64(tc);
+ assert64();
TLBIALL tlbiOp(EL3, true);
tlbiOp.broadcast(tc);
case MISCREG_TLBI_ALLE2:
case MISCREG_TLBI_ALLE2IS:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
tlbiOp(tc);
case MISCREG_TLBI_VMALLS12E1:
// @todo: handle VMID and stage 2 to enable Virtualization
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
tlbiOp(tc);
case MISCREG_TLBI_VMALLS12E1IS:
// @todo: handle VMID and stage 2 to enable Virtualization
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
tlbiOp.broadcast(tc);
case MISCREG_TLBI_VAE3_Xt:
case MISCREG_TLBI_VALE3_Xt:
{
- assert64(tc);
+ assert64();
TLBIMVA tlbiOp(EL3, true,
static_cast<Addr>(bits(newVal, 43, 0)) << 12,
case MISCREG_TLBI_VAE3IS_Xt:
case MISCREG_TLBI_VALE3IS_Xt:
{
- assert64(tc);
+ assert64();
TLBIMVA tlbiOp(EL3, true,
static_cast<Addr>(bits(newVal, 43, 0)) << 12,
case MISCREG_TLBI_VAE2_Xt:
case MISCREG_TLBI_VALE2_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 43, 0)) << 12,
case MISCREG_TLBI_VAE2IS_Xt:
case MISCREG_TLBI_VALE2IS_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 43, 0)) << 12,
case MISCREG_TLBI_VAE1_Xt:
case MISCREG_TLBI_VALE1_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
case MISCREG_TLBI_VAE1IS_Xt:
case MISCREG_TLBI_VALE1IS_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
// @todo: handle VMID to enable Virtualization
case MISCREG_TLBI_ASIDE1_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
// AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
case MISCREG_TLBI_ASIDE1IS_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
case MISCREG_TLBI_VAAE1_Xt:
case MISCREG_TLBI_VAALE1_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
case MISCREG_TLBI_VAAE1IS_Xt:
case MISCREG_TLBI_VAALE1IS_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
case MISCREG_TLBI_IPAS2E1_Xt:
case MISCREG_TLBI_IPAS2LE1_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 35, 0)) << 12);
case MISCREG_TLBI_IPAS2E1IS_Xt:
case MISCREG_TLBI_IPAS2LE1IS_Xt:
{
- assert64(tc);
- scr = readMiscReg(MISCREG_SCR, tc);
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 35, 0)) << 12);
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
- getGenericTimer(tc).setMiscReg(misc_reg, newVal);
+ getGenericTimer().setMiscReg(misc_reg, newVal);
break;
case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
- getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
+ getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
return;
case MISCREG_ZCR_EL3:
case MISCREG_ZCR_EL2:
case MISCREG_ZCR_EL1:
- tc->getDecoderPtr()->setSveLen(
- (getCurSveVecLenInBits(tc) >> 7) - 1);
+ tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
break;
}
}
}
BaseISADevice &
-ISA::getGenericTimer(ThreadContext *tc)
+ISA::getGenericTimer()
{
// We only need to create an ISA interface the first time we try
// to access the timer.
}
BaseISADevice &
-ISA::getGICv3CPUInterface(ThreadContext *tc)
+ISA::getGICv3CPUInterface()
{
panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
return *gicv3CpuInterface.get();
}
unsigned
-ISA::getCurSveVecLenInBits(ThreadContext *tc) const
+ISA::getCurSveVecLenInBits() const
{
if (!FullSystem) {
return sveVL * 128;
struct ArmISAParams;
struct DummyArmISADeviceParams;
-class ThreadContext;
class Checkpoint;
class EventManager;
}
}
- BaseISADevice &getGenericTimer(ThreadContext *tc);
- BaseISADevice &getGICv3CPUInterface(ThreadContext *tc);
-
+ BaseISADevice &getGenericTimer();
+ BaseISADevice &getGICv3CPUInterface();
private:
- inline void assert32(ThreadContext *tc) {
- CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
- assert(cpsr.width);
- }
-
- inline void assert64(ThreadContext *tc) {
- CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
- assert(!cpsr.width);
- }
+ void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width); }
+ void assert64() { assert(!((CPSR)readMiscReg(MISCREG_CPSR)).width); }
public:
- void clear(ThreadContext *tc);
+ void clear();
protected:
- void clear();
void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
void clear64(const ArmISAParams *p);
void initID32(const ArmISAParams *p);
public:
RegVal readMiscRegNoEffect(int misc_reg) const;
- RegVal readMiscReg(int misc_reg, ThreadContext *tc);
+ RegVal readMiscReg(int misc_reg);
void setMiscRegNoEffect(int misc_reg, RegVal val);
- void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
+ void setMiscReg(int misc_reg, RegVal val);
RegId
flattenRegId(const RegId& regId) const
return std::make_pair(lower, upper);
}
- unsigned getCurSveVecLenInBits(ThreadContext *tc) const;
+ unsigned getCurSveVecLenInBits() const;
unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
updateRegMap(tmp_cpsr);
}
- void startup(ThreadContext *tc);
+ void startup() override;
+
+ void setupThreadContext();
void takeOverFrom(ThreadContext *new_tc,
ThreadContext *old_tc) override;
return _vecRegRenameMode;
}
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
-
typedef ArmISAParams Params;
const Params *params() const;
protected:
using SimObject::SimObject;
+ ThreadContext *tc = nullptr;
+
public:
virtual void
takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
{}
+
+ virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
};
#endif // __ARCH_GENERIC_ISA_HH__
// Status to TCStatus depending on current thread
//template <class TC>
RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
+ISA::readMiscReg(int misc_reg, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
// be overwritten. Make sure to handle those particular registers
// with care!
void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
std::vector<BankType> bankType;
public:
- void clear(ThreadContext *tc) { clear(); }
-
- protected:
void clear();
public:
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
//template <class TC>
- RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
+ RegVal readMiscReg(int misc_reg, ThreadID tid = 0);
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
//template <class TC>
- void setMiscReg(int misc_reg, RegVal val,
- ThreadContext *tc, ThreadID tid=0);
+ void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0);
//////////////////////////////////////////////////////////
//
static std::string miscRegNames[NumMiscRegs];
public:
- void startup(ThreadContext *tc) {}
-
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
-
const Params *params() const;
ISA(Params *p);
RegId flattenRegId(const RegId& regId) const { return regId; }
- int
- flattenIntIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenFloatIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecPredIndex(int reg) const
- {
- return reg;
- }
-
+ int flattenIntIndex(int reg) const { return reg; }
+ int flattenFloatIndex(int reg) const { return reg; }
+ int flattenVecIndex(int reg) const { return reg; }
+ int flattenVecElemIndex(int reg) const { return reg; }
+ int flattenVecPredIndex(int reg) const { return reg; }
// dummy
- int
- flattenCCIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenMiscIndex(int reg) const
- {
- return reg;
- }
-
+ int flattenCCIndex(int reg) const { return reg; }
+ int flattenMiscIndex(int reg) const { return reg; }
};
}
public:
typedef PowerISAParams Params;
- void
- clear(ThreadContext *tc)
- {
- clear();
- }
-
- protected:
- void
- clear()
- {
- }
+ void clear() {}
public:
RegVal
}
RegVal
- readMiscReg(int misc_reg, ThreadContext *tc)
+ readMiscReg(int misc_reg)
{
fatal("Power does not currently have any misc regs defined\n");
return dummy;
}
void
- setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ setMiscReg(int misc_reg, RegVal val)
{
fatal("Power does not currently have any misc regs defined\n");
}
return reg;
}
- void startup(ThreadContext *tc) {}
-
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
-
const Params *params() const;
ISA(Params *p);
}
RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+ISA::readMiscReg(int misc_reg)
{
switch (misc_reg) {
case MISCREG_HARTID:
}
void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val)
{
if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
// Ignore writes to HPM counters for now
public:
typedef RiscvISAParams Params;
- void clear(ThreadContext *tc) { clear(); }
-
- protected:
void clear();
public:
RegVal readMiscRegNoEffect(int misc_reg) const;
- RegVal readMiscReg(int misc_reg, ThreadContext *tc);
+ RegVal readMiscReg(int misc_reg);
void setMiscRegNoEffect(int misc_reg, RegVal val);
- void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
+ void setMiscReg(int misc_reg, RegVal val);
RegId flattenRegId(const RegId ®Id) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
- void startup(ThreadContext *tc) {}
-
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
-
const Params *params() const;
ISA(Params *p);
ISA::ISA(Params *p) : BaseISA(p)
{
- tickCompare = NULL;
- sTickCompare = NULL;
- hSTickCompare = NULL;
-
clear();
}
}
RegVal
-ISA::readMiscReg(int miscReg, ThreadContext * tc)
+ISA::readMiscReg(int miscReg)
{
switch (miscReg) {
// tick and stick are aliased to each other in niagra
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
case MISCREG_HPSTATE:
- return readFSReg(miscReg, tc);
+ return readFSReg(miscReg);
}
return readMiscRegNoEffect(miscReg);
}
}
void
-ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
+ISA::setMiscReg(int miscReg, RegVal val)
{
RegVal new_val = val;
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
case MISCREG_HPSTATE:
- setFSReg(miscReg, val, tc);
+ setFSReg(miscReg, val);
return;
}
setMiscRegNoEffect(miscReg, new_val);
SERIALIZE_SCALAR(res_error_tail);
SERIALIZE_SCALAR(nres_error_head);
SERIALIZE_SCALAR(nres_error_tail);
+
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
- ThreadContext *tc = NULL;
- BaseCPU *cpu = NULL;
- int tc_num = 0;
- bool tick_intr_sched = true;
-
- if (tickCompare)
- tc = tickCompare->getTC();
- else if (sTickCompare)
- tc = sTickCompare->getTC();
- else if (hSTickCompare)
- tc = hSTickCompare->getTC();
- else
- tick_intr_sched = false;
-
- SERIALIZE_SCALAR(tick_intr_sched);
-
- if (tc) {
- cpu = tc->getCpuPtr();
- tc_num = cpu->findContext(tc);
- if (tickCompare && tickCompare->scheduled())
- tick_cmp = tickCompare->when();
- if (sTickCompare && sTickCompare->scheduled())
- stick_cmp = sTickCompare->when();
- if (hSTickCompare && hSTickCompare->scheduled())
- hstick_cmp = hSTickCompare->when();
-
- SERIALIZE_OBJPTR(cpu);
- SERIALIZE_SCALAR(tc_num);
- SERIALIZE_SCALAR(tick_cmp);
- SERIALIZE_SCALAR(stick_cmp);
- SERIALIZE_SCALAR(hstick_cmp);
- }
+ if (tickCompare && tickCompare->scheduled())
+ tick_cmp = tickCompare->when();
+ if (sTickCompare && sTickCompare->scheduled())
+ stick_cmp = sTickCompare->when();
+ if (hSTickCompare && hSTickCompare->scheduled())
+ hstick_cmp = hSTickCompare->when();
+
+ SERIALIZE_SCALAR(tick_cmp);
+ SERIALIZE_SCALAR(stick_cmp);
+ SERIALIZE_SCALAR(hstick_cmp);
}
void
UNSERIALIZE_SCALAR(nres_error_tail);
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
- ThreadContext *tc = NULL;
- BaseCPU *cpu = NULL;
- int tc_num;
- bool tick_intr_sched;
- UNSERIALIZE_SCALAR(tick_intr_sched);
- if (tick_intr_sched) {
- UNSERIALIZE_OBJPTR(cpu);
- if (cpu) {
- UNSERIALIZE_SCALAR(tc_num);
- UNSERIALIZE_SCALAR(tick_cmp);
- UNSERIALIZE_SCALAR(stick_cmp);
- UNSERIALIZE_SCALAR(hstick_cmp);
- tc = cpu->getContext(tc_num);
-
- if (tick_cmp) {
- tickCompare = new TickCompareEvent(this, tc);
- schedule(tickCompare, tick_cmp);
- }
- if (stick_cmp) {
- sTickCompare = new STickCompareEvent(this, tc);
- schedule(sTickCompare, stick_cmp);
- }
- if (hstick_cmp) {
- hSTickCompare = new HSTickCompareEvent(this, tc);
- schedule(hSTickCompare, hstick_cmp);
- }
- }
- }
+ UNSERIALIZE_SCALAR(tick_cmp);
+ UNSERIALIZE_SCALAR(stick_cmp);
+ UNSERIALIZE_SCALAR(hstick_cmp);
+ if (tick_cmp) {
+ tickCompare = new TickCompareEvent(this);
+ schedule(tickCompare, tick_cmp);
+ }
+ if (stick_cmp) {
+ sTickCompare = new STickCompareEvent(this);
+ schedule(sTickCompare, stick_cmp);
+ }
+ if (hstick_cmp) {
+ hSTickCompare = new HSTickCompareEvent(this);
+ schedule(hSTickCompare, hstick_cmp);
+ }
}
}
#include "arch/generic/isa.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/types.hh"
-#include "cpu/cpuevent.hh"
#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
- void setFSReg(int miscReg, RegVal val, ThreadContext *tc);
- RegVal readFSReg(int miscReg, ThreadContext * tc);
+ void setFSReg(int miscReg, RegVal val);
+ RegVal readFSReg(int miscReg);
// Update interrupt state on softint or pil change
- void checkSoftInt(ThreadContext *tc);
+ void checkSoftInt();
/** Process a tick compare event and generate an interrupt on the cpu if
* appropriate. */
- void processTickCompare(ThreadContext *tc);
- void processSTickCompare(ThreadContext *tc);
- void processHSTickCompare(ThreadContext *tc);
+ void processTickCompare();
+ void processSTickCompare();
+ void processHSTickCompare();
- typedef CpuEventWrapper<ISA,
- &ISA::processTickCompare> TickCompareEvent;
- TickCompareEvent *tickCompare;
+ typedef EventWrapper<ISA, &ISA::processTickCompare> TickCompareEvent;
+ TickCompareEvent *tickCompare = nullptr;
- typedef CpuEventWrapper<ISA,
- &ISA::processSTickCompare> STickCompareEvent;
- STickCompareEvent *sTickCompare;
+ typedef EventWrapper<ISA, &ISA::processSTickCompare> STickCompareEvent;
+ STickCompareEvent *sTickCompare = nullptr;
- typedef CpuEventWrapper<ISA,
- &ISA::processHSTickCompare> HSTickCompareEvent;
- HSTickCompareEvent *hSTickCompare;
+ typedef EventWrapper<ISA, &ISA::processHSTickCompare> HSTickCompareEvent;
+ HSTickCompareEvent *hSTickCompare = nullptr;
static const int NumGlobalRegs = 8;
static const int NumWindowedRegs = 24;
public:
- void clear(ThreadContext *tc) { clear(); }
+ void clear();
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void startup(ThreadContext *tc) {}
-
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
-
protected:
- void clear();
bool isHyperPriv() { return hpstate.hpriv; }
bool isPriv() { return hpstate.hpriv || pstate.priv; }
bool isNonPriv() { return !isPriv(); }
public:
RegVal readMiscRegNoEffect(int miscReg) const;
- RegVal readMiscReg(int miscReg, ThreadContext *tc);
+ RegVal readMiscReg(int miscReg);
void setMiscRegNoEffect(int miscReg, RegVal val);
- void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
+ void setMiscReg(int miscReg, RegVal val);
RegId
flattenRegId(const RegId& regId) const
return flatIndex;
}
- int
- flattenFloatIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecPredIndex(int reg) const
- {
- return reg;
- }
+ int flattenFloatIndex(int reg) const { return reg; }
+ int flattenVecIndex(int reg) const { return reg; }
+ int flattenVecElemIndex(int reg) const { return reg; }
+ int flattenVecPredIndex(int reg) const { return reg; }
// dummy
- int
- flattenCCIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenMiscIndex(int reg) const
- {
- return reg;
- }
+ int flattenCCIndex(int reg) const { return reg; }
+ int flattenMiscIndex(int reg) const { return reg; }
typedef SparcISAParams Params;
void
-ISA::checkSoftInt(ThreadContext *tc)
+ISA::checkSoftInt()
{
BaseCPU *cpu = tc->getCpuPtr();
}
void
-ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, RegVal val)
{
BaseCPU *cpu = tc->getCpuPtr();
switch (miscReg) {
/* Full system only ASRs */
case MISCREG_SOFTINT:
- setMiscRegNoEffect(miscReg, val);;
- checkSoftInt(tc);
+ setMiscRegNoEffect(miscReg, val);
+ checkSoftInt();
break;
case MISCREG_SOFTINT_CLR:
- return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
+ return setMiscReg(MISCREG_SOFTINT, ~val & softint);
case MISCREG_SOFTINT_SET:
- return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
+ return setMiscReg(MISCREG_SOFTINT, val | softint);
case MISCREG_TICK_CMPR:
if (tickCompare == NULL)
- tickCompare = new TickCompareEvent(this, tc);
+ tickCompare = new TickCompareEvent(this);
setMiscRegNoEffect(miscReg, val);
if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
cpu->deschedule(tickCompare);
case MISCREG_STICK_CMPR:
if (sTickCompare == NULL)
- sTickCompare = new STickCompareEvent(this, tc);
+ sTickCompare = new STickCompareEvent(this);
setMiscRegNoEffect(miscReg, val);
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
cpu->deschedule(sTickCompare);
case MISCREG_PIL:
setMiscRegNoEffect(miscReg, val);
- checkSoftInt(tc);
+ checkSoftInt();
break;
case MISCREG_HVER:
case MISCREG_HSTICK_CMPR:
if (hSTickCompare == NULL)
- hSTickCompare = new HSTickCompareEvent(this, tc);
+ hSTickCompare = new HSTickCompareEvent(this);
setMiscRegNoEffect(miscReg, val);
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
cpu->deschedule(hSTickCompare);
}
RegVal
-ISA::readFSReg(int miscReg, ThreadContext * tc)
+ISA::readFSReg(int miscReg)
{
uint64_t temp;
}
void
-ISA::processTickCompare(ThreadContext *tc)
+ISA::processTickCompare()
{
panic("tick compare not implemented\n");
}
void
-ISA::processSTickCompare(ThreadContext *tc)
+ISA::processSTickCompare()
{
BaseCPU *cpu = tc->getCpuPtr();
DPRINTF(Timer, "STick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
- setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
+ setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16));
}
} else {
cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
}
void
-ISA::processHSTickCompare(ThreadContext *tc)
+ISA::processHSTickCompare()
{
BaseCPU *cpu = tc->getCpuPtr();
DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
- setMiscReg(MISCREG_HINTP, 1, tc);
+ setMiscReg(MISCREG_HINTP, 1);
}
// Need to do something to cause interrupt to happen here !!! @todo
} else {
void
ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
- SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
- ThreadContext *tc)
+ SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
{
HandyM5Reg m5reg = 0;
if (efer.lma) {
}
RegVal
-ISA::readMiscReg(int miscReg, ThreadContext * tc)
+ISA::readMiscReg(int miscReg)
{
if (miscReg == MISCREG_TSC) {
return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
}
void
-ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
+ISA::setMiscReg(int miscReg, RegVal val)
{
RegVal newVal = val;
switch(miscReg)
newCR0,
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
- regVal[MISCREG_RFLAGS],
- tc);
+ regVal[MISCREG_RFLAGS]);
}
break;
case MISCREG_CR2:
regVal[MISCREG_CR0],
newCSAttr,
regVal[MISCREG_SS_ATTR],
- regVal[MISCREG_RFLAGS],
- tc);
+ regVal[MISCREG_RFLAGS]);
}
break;
case MISCREG_SS_ATTR:
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
val,
- regVal[MISCREG_RFLAGS],
- tc);
+ regVal[MISCREG_RFLAGS]);
break;
// These segments always actually use their bases, or in other words
// their effective bases must stay equal to their actual bases.
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
- regVal[MISCREG_RFLAGS],
- tc);
+ regVal[MISCREG_RFLAGS]);
return;
default:
break;
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
- regVal[MISCREG_RFLAGS],
- NULL);
+ regVal[MISCREG_RFLAGS]);
}
void
-ISA::startup(ThreadContext *tc)
+ISA::setThreadContext(ThreadContext *_tc)
{
+ BaseISA::setThreadContext(_tc);
tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
}
protected:
RegVal regVal[NUM_MISCREGS];
void updateHandyM5Reg(Efer efer, CR0 cr0,
- SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
- ThreadContext *tc);
- void clear();
+ SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
public:
- typedef X86ISAParams Params;
+ void clear();
- void clear(ThreadContext *tc) { clear(); }
+ typedef X86ISAParams Params;
ISA(Params *p);
const Params *params() const;
RegVal readMiscRegNoEffect(int miscReg) const;
- RegVal readMiscReg(int miscReg, ThreadContext *tc);
+ RegVal readMiscReg(int miscReg);
void setMiscRegNoEffect(int miscReg, RegVal val);
- void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
+ void setMiscReg(int miscReg, RegVal val);
RegId
flattenRegId(const RegId& regId) const
return regId;
}
- int
- flattenIntIndex(int reg) const
- {
- return reg & ~IntFoldBit;
- }
+ int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }
int
flattenFloatIndex(int reg) const
return reg;
}
- int
- flattenVecIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecPredIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenCCIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenMiscIndex(int reg) const
- {
- return reg;
- }
+ int flattenVecIndex(int reg) const { return reg; }
+ int flattenVecElemIndex(int reg) const { return reg; }
+ int flattenVecPredIndex(int reg) const { return reg; }
+ int flattenCCIndex(int reg) const { return reg; }
+ int flattenMiscIndex(int reg) const { return reg; }
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void startup(ThreadContext *tc);
-
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
-
+ void setThreadContext(ThreadContext *_tc) override;
};
}
Source('activity.cc')
Source('base.cc')
-Source('cpuevent.cc')
Source('exetrace.cc')
Source('exec_context.cc')
Source('func_unit.cc')
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/checker/cpu.hh"
-#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
#include "debug/Mwait.hh"
tc->getProcessPtr()->assignThreadContext(tc->contextId());
interrupts[tid]->setThreadContext(tc);
+ tc->getIsaPtr()->setThreadContext(tc);
}
}
ThreadContext *newTC = threadContexts[i];
ThreadContext *oldTC = oldCPU->threadContexts[i];
- newTC->takeOverFrom(oldTC);
+ newTC->getIsaPtr()->setThreadContext(newTC);
- CpuEvent::replaceThreadContext(oldTC, newTC);
+ newTC->takeOverFrom(oldTC);
assert(newTC->contextId() == oldTC->contextId());
assert(newTC->threadId() == oldTC->threadId());
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "cpu/cpuevent.hh"
-
-/** Static list of all CpuEvent objects so we can modify their thread
- * contexts as needed. */
-CpuEvent::CpuEventList CpuEvent::cpuEventList;
-
-CpuEvent::~CpuEvent()
-{
- CpuEventList::iterator i;
-
- // delete the event from the global list
- for (i = cpuEventList.begin(); i != cpuEventList.end(); ) {
- if (*i == this)
- i = cpuEventList.erase(i);
- else
- i++;
- }
-}
-
-void
-CpuEvent::replaceThreadContext(ThreadContext *oldTc, ThreadContext *newTc)
-{
- CpuEventList::iterator i;
-
- // Update any events that have the old thread context with the new thread
- // context
- for (i = cpuEventList.begin(); i != cpuEventList.end(); i++) {
- if ((*i)->tc == oldTc)
- (*i)->tc = newTc;
- }
-}
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_CPUEVENT_HH__
-#define __CPU_CPUEVENT_HH__
-
-#include <vector>
-
-#include "sim/eventq.hh"
-
-class ThreadContext;
-
-/**
- * This class creates a global list of events that need a pointer to a
- * thread context. When a switchover takes place the events can be
- * migrated to the new thread context, otherwise you could have a wake
- * timer interrupt go off on a switched out cpu or other unfortunate
- * events. This object MUST be dynamically allocated to avoid it being
- * deleted after a cpu switch happens.
- */
-class CpuEvent : public Event
-{
- protected:
- /** type of global list of cpu events. */
- typedef std::vector<CpuEvent *> CpuEventList;
-
- /** Static list of cpu events that is searched every time a cpu switch
- * happens. */
- static CpuEventList cpuEventList;
-
- /** The thread context that is switched to the new cpus. */
- ThreadContext *tc;
-
- public:
- CpuEvent(ThreadContext *_tc, Priority p = Default_Pri)
- : Event(p), tc(_tc)
- { cpuEventList.push_back(this); }
-
- /** delete the cpu event from the global list. */
- ~CpuEvent();
-
- /** Update all events switching old tc to new tc.
- * @param oldTc the old thread context we are switching from
- * @param newTc the new thread context we are switching to.
- */
- static void replaceThreadContext(ThreadContext *oldTc,
- ThreadContext *newTc);
- ThreadContext* getTC() { return tc; }
-};
-
-template <class T, void (T::* F)(ThreadContext *tc)>
-class CpuEventWrapper : public CpuEvent
-{
- private:
- T *object;
-
- public:
- CpuEventWrapper(T *obj, ThreadContext *_tc, Priority p = Default_Pri)
- : CpuEvent(_tc, p), object(obj)
- { }
- void process() { (object->*F)(tc); }
-};
-
-#endif // __CPU_CPUEVENT_HH__
-
inform("KVM: Coalesced not supported by host OS\n");
}
- thread->startup();
-
Event *startupEvent(
new EventFunctionWrapper([this]{ startupThread(); }, name(), true));
schedule(startupEvent, curTick());
BaseCPU::startup();
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- threads[tid]->startup();
+ for (ThreadID tid = 0; tid < numThreads; tid++)
pipeline->wakeupFetch(tid);
- }
}
DrainState
FullO3CPU<Impl>::startup()
{
BaseCPU::startup();
- for (int tid = 0; tid < numThreads; ++tid)
- isa[tid]->startup(threadContexts[tid]);
fetch.startupStage();
decode.startupStage();
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
miscRegfileReads++;
- return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
+ return this->isa[tid]->readMiscReg(misc_reg);
}
template <class Impl>
FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
miscRegfileWrites++;
- this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
+ this->isa[tid]->setMiscReg(misc_reg, val);
}
template <class Impl>
void
O3ThreadContext<Impl>::clearArchRegs()
{
- cpu->isa[thread->threadId()]->clear(this);
+ cpu->isa[thread->threadId()]->clear();
}
template <class Impl>
}
}
}
-
-void
-BaseSimpleCPU::startup()
-{
- BaseCPU::startup();
- for (auto& t_info : threadInfo)
- t_info->thread->startup();
-}
void regStats() override;
void resetStats() override;
- void startup() override;
-
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
Request::Flags flags,
const std::vector<bool>& byte_enable =
::unserialize(*this, cp);
}
-void
-SimpleThread::startup()
-{
- isa->startup(this);
-}
-
void
SimpleThread::dumpFuncProfile()
{
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void startup();
/***************************************************************
* SimpleThread functions to provide CPU with access to various
for (auto &pred_reg: vecPredRegs)
pred_reg.reset();
ccRegs.fill(0);
- isa->clear(this);
+ isa->clear();
}
//
RegVal
readMiscReg(RegIndex misc_reg) override
{
- return isa->readMiscReg(misc_reg, this);
+ return isa->readMiscReg(misc_reg);
}
void
void
setMiscReg(RegIndex misc_reg, RegVal val) override
{
- return isa->setMiscReg(misc_reg, val, this);
+ return isa->setMiscReg(misc_reg, val);
}
RegId
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